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core/udp: simplify LiteEthUDPCrossbar.get_port when used with cdc

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This commit is contained in:
Florent Kermarrec 2017-07-01 13:14:13 +02:00
parent b870d13d96
commit 1127e3a615
1 changed files with 29 additions and 28 deletions
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57
liteeth/core/udp.py
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@ -30,46 +30,47 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
def __init__(self): def __init__(self):
LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port") LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port")
def get_port(self, udp_port, dw=8, cd=None): def get_port(self, udp_port, dw=8, cd="sys"):
if udp_port in self.users.keys(): if udp_port in self.users.keys():
raise ValueError("Port {0:#x} already assigned".format(udp_port)) raise ValueError("Port {0:#x} already assigned".format(udp_port))
user_port = LiteEthUDPUserPort(dw) user_port = LiteEthUDPUserPort(dw)
internal_port = LiteEthUDPUserPort(8) internal_port = LiteEthUDPUserPort(8)
# tx
tx_stream = user_port.sink
if cd is not "sys":
tx_cdc = stream.AsyncFIFO(eth_udp_user_description(user_port.dw), 4)
tx_cdc = ClockDomainsRenamer({"write": cd, "read": "sys"})(tx_cdc)
self.submodules += tx_cdc
self.comb += tx_stream.connect(tx_cdc.sink)
tx_stream = tx_cdc.source
if dw != 8: if dw != 8:
# tx
tx_converter = stream.StrideConverter(eth_udp_user_description(user_port.dw), tx_converter = stream.StrideConverter(eth_udp_user_description(user_port.dw),
eth_udp_user_description(8)) eth_udp_user_description(8))
self.submodules += tx_converter self.submodules += tx_converter
if cd is not None: self.comb += tx_stream.connect(tx_converter.sink)
tx_cdc = stream.AsyncFIFO(eth_udp_user_description(user_port.dw), 4) tx_stream = tx_converter.source
tx_cdc = ClockDomainsRenamer({"write": cd, "read": "sys"})(tx_cdc) self.comb += tx_stream.connect(internal_port.sink)
self.submodules += tx_cdc
self.comb += [
user_port.sink.connect(tx_cdc.sink),
tx_cdc.source.connect(tx_converter.sink)
]
else:
self.comb += user_port.sink.connect(tx_converter.sink)
self.comb += tx_converter.source.connect(internal_port.sink)
# rx # rx
rx_stream = internal_port.source
if dw != 8:
rx_converter = stream.StrideConverter(eth_udp_user_description(8), rx_converter = stream.StrideConverter(eth_udp_user_description(8),
eth_udp_user_description(user_port.dw)) eth_udp_user_description(user_port.dw))
self.submodules += rx_converter self.submodules += rx_converter
self.comb += internal_port.source.connect(rx_converter.sink) self.comb += rx_stream.connect(rx_converter.sink)
if cd is not None: rx_stream = rx_converter.source
rx_cdc = stream.AsyncFIFO(eth_udp_user_description(user_port.dw), 4) if cd is not "sys":
rx_cdc = ClockDomainsRenamer({"write": "sys", "read": cd})(rx_cdc) rx_cdc = stream.AsyncFIFO(eth_udp_user_description(user_port.dw), 4)
self.submodules += rx_cdc rx_cdc = ClockDomainsRenamer({"write": "sys", "read": cd})(rx_cdc)
self.comb += [ self.submodules += rx_cdc
rx_converter.source.connect(rx_cdc.sink), self.comb += rx_stream.connect(rx_cdc.sink)
rx_cdc.source.connect(user_port.source) rx_stream = rx_cdc.source
] self.comb += rx_stream.connect(user_port.source)
else:
self.comb += rx_converter.source.connect(user_port.source) self.users[udp_port] = internal_port
self.users[udp_port] = internal_port
else:
self.users[udp_port] = user_port
return user_port return user_port
# udp tx # udp tx