mac/core: Avoid passing core_dw/phy_dw to add_tx/rx_converter.
This commit is contained in:
Florent Kermarrec
parent
6204994bad
commit
11555d43cb
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@ -28,9 +28,10 @@ class LiteEthMACCore(Module, AutoCSR):
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self.source = stream.Endpoint(eth_phy_description(dw))
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# Parameters.
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core_dw = dw
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if core_dw < phy.dw:
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raise ValueError("Core data width({}) must be larger than PHY data width({})".format(core_dw, phy.dw))
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self.core_dw = core_dw = dw
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self.phy_dw = phy_dw = phy.dw
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if core_dw < phy_dw:
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raise ValueError("Core data width({}) must be larger than PHY data width({})".format(core_dw, phy_dw))
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if with_sys_datapath:
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cd_tx = "sys"
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@ -39,7 +40,7 @@ class LiteEthMACCore(Module, AutoCSR):
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else:
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cd_tx = "eth_tx"
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cd_rx = "eth_rx"
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datapath_dw = phy.dw
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datapath_dw = phy_dw
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# CSRs.
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if with_preamble_crc:
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@ -56,16 +57,16 @@ class LiteEthMACCore(Module, AutoCSR):
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# Late sys conversion.
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if not with_sys_datapath:
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self.add_tx_converter(core_dw, phy.dw)
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self.add_tx_converter()
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# Padding
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# Padding.
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if with_padding:
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tx_padding = padding.LiteEthMACPaddingInserter(datapath_dw, (eth_min_frame_length - eth_fcs_length))
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tx_padding = ClockDomainsRenamer(cd_tx)(tx_padding)
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self.submodules += tx_padding
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tx_datapath.append(tx_padding)
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# Preamble / CRC
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# Preamble / CRC.
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if with_preamble_crc:
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# CRC insert.
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tx_crc = crc.LiteEthMACCRC32Inserter(eth_phy_description(datapath_dw))
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@ -80,7 +81,7 @@ class LiteEthMACCore(Module, AutoCSR):
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self.submodules += tx_preamble
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tx_datapath.append(tx_preamble)
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# Interpacket gap
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# Interpacket gap.
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tx_gap = gap.LiteEthMACGap(datapath_dw)
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tx_gap = ClockDomainsRenamer(cd_tx)(tx_gap)
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self.submodules += tx_gap
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@ -88,7 +89,7 @@ class LiteEthMACCore(Module, AutoCSR):
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# Early sys conversion.
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if with_sys_datapath:
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self.add_tx_converter(core_dw, phy.dw)
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self.add_tx_converter(core_dw, phy_dw)
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# PHY.
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tx_datapath.append(phy)
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@ -105,9 +106,9 @@ class LiteEthMACCore(Module, AutoCSR):
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# Early sys conversion.
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if with_sys_datapath:
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self.add_rx_converter(core_dw, phy.dw)
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self.add_rx_converter()
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# Preamble / CRC
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# Preamble / CRC.
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if with_preamble_crc:
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# Preamble check.
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rx_preamble = preamble.LiteEthMACPreambleChecker(datapath_dw)
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@ -148,7 +149,7 @@ class LiteEthMACCore(Module, AutoCSR):
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# Late sys conversion.
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if not with_sys_datapath:
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self.add_rx_converter(core_dw, phy.dw)
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self.add_rx_converter()
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# Source.
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rx_datapath.append(self.source)
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@ -156,9 +157,9 @@ class LiteEthMACCore(Module, AutoCSR):
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# Data-Path.
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self.submodules.rx_pipeline = stream.Pipeline(*rx_datapath)
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def add_tx_converter(self, dw, phy_dw):
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def add_tx_converter(self):
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# Cross Domain Crossing.
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tx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw),
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tx_cdc = stream.ClockDomainCrossing(eth_phy_description(self.core_dw),
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cd_from = "sys",
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cd_to = "eth_tx",
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depth = 32)
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@ -166,40 +167,40 @@ class LiteEthMACCore(Module, AutoCSR):
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self.tx_datapath.append(tx_cdc)
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# Converters.
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if dw != phy_dw:
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if self.core_dw != self.phy_dw:
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tx_converter = stream.StrideConverter(
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description_from = eth_phy_description(dw),
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description_to = eth_phy_description(phy_dw))
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description_from = eth_phy_description(self.core_dw),
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description_to = eth_phy_description(self.phy_dw))
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tx_converter = ClockDomainsRenamer("eth_tx")(tx_converter)
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self.submodules += tx_converter
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self.tx_datapath.append(tx_converter)
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# Delimiters.
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if dw != 8:
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tx_last_be = last_be.LiteEthMACTXLastBE(phy_dw)
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if self.core_dw != 8:
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tx_last_be = last_be.LiteEthMACTXLastBE(self.phy_dw)
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tx_last_be = ClockDomainsRenamer("eth_tx")(tx_last_be)
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self.submodules += tx_last_be
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self.tx_datapath.append(tx_last_be)
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def add_rx_converter(self, dw, phy_dw):
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def add_rx_converter(self):
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# Delimiters.
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if dw != 8:
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rx_last_be = last_be.LiteEthMACRXLastBE(phy_dw)
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if self.core_dw != 8:
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rx_last_be = last_be.LiteEthMACRXLastBE(self.phy_dw)
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rx_last_be = ClockDomainsRenamer("eth_rx")(rx_last_be)
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self.submodules += rx_last_be
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self.rx_datapath.append(rx_last_be)
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# Converters.
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if dw != phy_dw:
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if self.core_dw != self.phy_dw:
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rx_converter = stream.StrideConverter(
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description_from = eth_phy_description(phy_dw),
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description_to = eth_phy_description(dw))
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description_from = eth_phy_description(self.phy_dw),
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description_to = eth_phy_description(self.core_dw))
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rx_converter = ClockDomainsRenamer("eth_rx")(rx_converter)
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self.submodules += rx_converter
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self.rx_datapath.append(rx_converter)
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# Cross Domain Crossing
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rx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw),
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rx_cdc = stream.ClockDomainCrossing(eth_phy_description(self.core_dw),
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cd_from = "eth_rx",
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cd_to = "sys",
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depth = 32)
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