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frontend/stream: Add data_width support.

This commit is contained in:
Florent Kermarrec 2022-01-14 18:38:21 +01:00
parent 6a6bc28869
commit 14edaaeec2
1 changed files with 13 additions and 13 deletions
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26
liteeth/frontend/stream.py
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@ -6,12 +6,12 @@
from liteeth.common import *
# Steam 2 UDP TX -----------------------------------------------------------------------------------
# Stream to UDP TX -----------------------------------------------------------------------------------
class LiteEthStream2UDPTX(Module):
def __init__(self, ip_address, udp_port, fifo_depth=None, send_level=1):
self.sink = sink = stream.Endpoint(eth_tty_description(8))
self.source = source = stream.Endpoint(eth_udp_user_description(8))
def __init__(self, ip_address, udp_port, data_width=8, fifo_depth=None, send_level=1):
self.sink = sink = stream.Endpoint(eth_tty_description(data_width))
self.source = source = stream.Endpoint(eth_udp_user_description(data_width))
# # #
@ -31,7 +31,7 @@ class LiteEthStream2UDPTX(Module):
level = Signal(max=fifo_depth+1)
counter = Signal(max=fifo_depth+1)
self.submodules.fifo = fifo = stream.SyncFIFO([("data", 8)], fifo_depth)
self.submodules.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth)
self.comb += sink.connect(fifo.sink)
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
@ -62,9 +62,9 @@ class LiteEthStream2UDPTX(Module):
# UDP to Stream RX ---------------------------------------------------------------------------------
class LiteEthUDP2StreamRX(Module):
def __init__(self, ip_address=None, udp_port=None, fifo_depth=None):
self.sink = sink = stream.Endpoint(eth_udp_user_description(8))
self.source = source = stream.Endpoint(eth_tty_description(8))
def __init__(self, ip_address=None, udp_port=None, data_width=8, fifo_depth=None):
self.sink = sink = stream.Endpoint(eth_udp_user_description(data_width))
self.source = source = stream.Endpoint(eth_tty_description(data_width))
# # #
@ -87,7 +87,7 @@ class LiteEthUDP2StreamRX(Module):
sink.ready.eq(source.ready | ~valid)
]
else:
self.submodules.fifo = fifo = stream.SyncFIFO([("data", 8)], fifo_depth)
self.submodules.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth)
self.comb += [
sink.connect(fifo.sink, keep={"last", "data"}),
fifo.sink.valid.eq(sink.valid & valid),
@ -98,10 +98,10 @@ class LiteEthUDP2StreamRX(Module):
# UDP Streamer -------------------------------------------------------------------------------------
class LiteEthUDPStreamer(Module):
def __init__(self, udp, ip_address, udp_port, rx_fifo_depth=64, tx_fifo_depth=64):
self.submodules.tx = tx = LiteEthStream2UDPTX(ip_address, udp_port, tx_fifo_depth)
self.submodules.rx = rx = LiteEthUDP2StreamRX(ip_address, udp_port, rx_fifo_depth)
udp_port = udp.crossbar.get_port(udp_port, dw=8)
def __init__(self, udp, ip_address, udp_port, data_width=8, rx_fifo_depth=64, tx_fifo_depth=64):
self.submodules.tx = tx = LiteEthStream2UDPTX(ip_address, udp_port, data_width, tx_fifo_depth)
self.submodules.rx = rx = LiteEthUDP2StreamRX(ip_address, udp_port, data_width, rx_fifo_depth)
udp_port = udp.crossbar.get_port(udp_port, dw=data_width)
self.comb += [
tx.source.connect(udp_port.sink),
udp_port.source.connect(rx.sink)