liteeth/gen: Cosmetic cleanup in 1000BaseX.
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1bbb735f9f
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@ -293,12 +293,15 @@ class PHYCore(SoCMini):
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with_hw_init_reset = False) # FIXME: required since sys_clk = eth_rx_clk.
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with_hw_init_reset = False) # FIXME: required since sys_clk = eth_rx_clk.
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# SGMII.
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# SGMII.
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elif phy in [
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elif phy in [
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# 7-Series GTP/GTX.
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liteeth_phys.A7_1000BASEX,
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liteeth_phys.A7_1000BASEX,
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liteeth_phys.A7_2500BASEX,
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liteeth_phys.A7_2500BASEX,
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liteeth_phys.K7_1000BASEX,
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liteeth_phys.K7_1000BASEX,
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liteeth_phys.K7_2500BASEX,
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liteeth_phys.K7_2500BASEX,
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# Ultrascale GTHE3.
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liteeth_phys.KU_1000BASEX,
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liteeth_phys.KU_1000BASEX,
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liteeth_phys.KU_2500BASEX,
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liteeth_phys.KU_2500BASEX,
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# Ultrascale+ GTHE4/GTYE4
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liteeth_phys.USP_GTH_1000BASEX,
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liteeth_phys.USP_GTH_1000BASEX,
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liteeth_phys.USP_GTH_2500BASEX,
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liteeth_phys.USP_GTH_2500BASEX,
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liteeth_phys.USP_GTY_1000BASEX,
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liteeth_phys.USP_GTY_1000BASEX,
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@ -352,13 +355,17 @@ class PHYCore(SoCMini):
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# Other 7-Series/Ultrascale(+).
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# Other 7-Series/Ultrascale(+).
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else:
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else:
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ethphy = phy(
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ethphy = phy(
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refclk_or_clk_pads = ethphy_pads.refclk,
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# General.
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data_pads = ethphy_pads,
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data_pads = ethphy_pads,
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sys_clk_freq = self.clk_freq,
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sys_clk_freq = self.clk_freq,
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refclk_freq = core_config.get("refclk_freq", 200e6),
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with_csr = False,
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with_csr = False,
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rx_polarity = core_config.get("phy_rx_polarity", 0),
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# Clocking.
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refclk_or_clk_pads = ethphy_pads.refclk,
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refclk_freq = core_config.get("refclk_freq", 200e6),
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# TX.
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tx_polarity = core_config.get("phy_tx_polarity", 0),
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tx_polarity = core_config.get("phy_tx_polarity", 0),
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# RX.
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rx_polarity = core_config.get("phy_rx_polarity", 0),
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)
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)
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self.comb += [
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self.comb += [
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ethphy.reset.eq(ethphy_pads.rst),
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ethphy.reset.eq(ethphy_pads.rst),
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