phy/trionrgmii: Fix source.last.
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@ -105,9 +105,9 @@ class LiteEthPHYRGMIIRX(Module):
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self.comb += last.eq(~pads.rx_ctl & rx_ctl_d)
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self.comb += last.eq(~pads.rx_ctl & rx_ctl_d)
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self.sync += [
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self.sync += [
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source.valid.eq(rx_ctl_d),
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source.valid.eq(rx_ctl_d),
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source.data.eq(rx_data),
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source.data.eq(rx_data)
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source.last.eq(last),
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]
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]
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self.comb += source.last.eq(last)
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class LiteEthPHYRGMIICRG(Module, AutoCSR):
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class LiteEthPHYRGMIICRG(Module, AutoCSR):
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def __init__(self, platform, clock_pads, with_hw_init_reset, hw_reset_cycles=256):
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def __init__(self, platform, clock_pads, with_hw_init_reset, hw_reset_cycles=256):
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