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example_design/targets/core: cleanup
This commit is contained in:
Florent Kermarrec
parent
36399d65da
commit
1dae2b802c
2 changed files with 90 additions and 79 deletions
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@ -3,17 +3,17 @@ cores:
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mkdir cores
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python3 core.py --phy MII --core mac
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cp liteeth/gateware/liteeth.v cores/liteeth_mac_wishbone_mii.v
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cp liteeth/gateware/liteeth.v cores/liteeth_mac_mii.v
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python3 core.py --phy GMII --core mac
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cp liteeth/gateware/liteeth.v cores/liteeth_mac_wishbone_gmii.v
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cp liteeth/gateware/liteeth.v cores/liteeth_mac_gmii.v
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python3 core.py --phy RGMII --core mac
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cp liteeth/gateware/liteeth.v cores/liteeth_mac_wishbone_rgmii.v
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cp liteeth/gateware/liteeth.v cores/liteeth_mac_rgmii.v
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python3 core.py --phy MII --core udp
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cp liteeth/gateware/liteeth.v cores/liteeth_udpip_mii.v
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cp liteeth/gateware/liteeth.v cores/liteeth_udp_mii.v
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python3 core.py --phy GMII --core udp
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cp liteeth/gateware/liteeth.v cores/liteeth_udpip_gmii.v
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cp liteeth/gateware/liteeth.v cores/liteeth_udp_gmii.v
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python3 core.py --phy RGMII --core udp
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cp liteeth/gateware/liteeth.v cores/liteeth_udpip_rgmii.v
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cp liteeth/gateware/liteeth.v cores/liteeth_udp_rgmii.v
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.PHONY: cores
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@ -149,29 +149,9 @@ class CorePlatform(XilinxPlatform):
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def do_finalize(self, *args, **kwargs):
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pass
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class WishboneBridge(Module):
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def __init__(self, interface):
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self.wishbone = interface
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class Core(SoCCore):
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csr_peripherals = (
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"ethphy",
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"ethmac"
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)
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csr_map = dict((n, v) for v, n in enumerate(csr_peripherals, start=16))
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csr_map.update(SoCCore.csr_map)
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interrupt_map = {
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"ethmac": 2,
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}
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interrupt_map.update(SoCCore.interrupt_map)
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mem_map = {
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"ethmac": 0x50000000
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}
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mem_map.update(SoCCore.mem_map)
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def __init__(self, phy, core, clk_freq, mac_address, ip_address, udp_port):
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class PHYCore(SoCCore):
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def __init__(self, phy, clk_freq):
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platform = CorePlatform()
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SoCCore.__init__(self, platform,
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clk_freq=clk_freq,
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@ -199,55 +179,84 @@ class Core(SoCCore):
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else:
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ValueError("Unsupported " + phy + " PHY");
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# core
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if core == "mac":
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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self.add_cpu_or_bridge(WishboneBridge(platform.request("wishbone")))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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elif core == "udp":
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self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), clk_freq)
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udp_port = self.core.udp.crossbar.get_port(udp_port, 8)
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# XXX avoid manual connect
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udp_sink = platform.request("udp_sink")
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self.comb += [
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# control
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udp_port.sink.stb.eq(udp_sink.stb),
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udp_port.sink.sop.eq(udp_sink.sop),
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udp_port.sink.eop.eq(udp_sink.eop),
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udp_sink.ack.eq(udp_port.sink.ack),
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class MACCore(PHYCore):
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csr_peripherals = (
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"ethphy",
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"ethmac"
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)
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csr_map = dict((n, v) for v, n in enumerate(csr_peripherals, start=16))
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csr_map.update(SoCCore.csr_map)
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# param
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udp_port.sink.src_port.eq(udp_sink.src_port),
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udp_port.sink.dst_port.eq(udp_sink.dst_port),
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udp_port.sink.ip_address.eq(udp_sink.ip_address),
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udp_port.sink.length.eq(udp_sink.length),
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interrupt_map = {
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"ethmac": 2,
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}
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interrupt_map.update(SoCCore.interrupt_map)
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# payload
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udp_port.sink.data.eq(udp_sink.data),
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udp_port.sink.error.eq(udp_sink.error)
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]
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udp_source = platform.request("udp_source")
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self.comb += [
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# control
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udp_source.stb.eq(udp_port.source.stb),
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udp_source.sop.eq(udp_port.source.sop),
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udp_source.eop.eq(udp_port.source.eop),
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udp_port.source.ack.eq(udp_source.ack),
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mem_map = {
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"ethmac": 0x50000000
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}
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mem_map.update(SoCCore.mem_map)
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def __init__(self, phy, clk_freq):
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PHYCore.__init__(self, phy, clk_freq)
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# param
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udp_source.src_port.eq(udp_port.source.src_port),
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udp_source.dst_port.eq(udp_port.source.dst_port),
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udp_source.ip_address.eq(udp_port.source.ip_address),
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udp_source.length.eq(udp_port.source.length),
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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class _WishboneBridge(Module):
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def __init__(self, interface):
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self.wishbone = interface
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self.add_cpu_or_bridge(_WishboneBridge(self.platform.request("wishbone")))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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class UDPCore(PHYCore):
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def __init__(self, phy, clk_freq, mac_address, ip_address, port):
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PHYCore.__init__(self, phy, clk_freq)
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self.submodules.core = LiteEthUDPIPCore(self.ethphy, mac_address, convert_ip(ip_address), clk_freq)
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udp_port = self.core.udp.crossbar.get_port(port, 8)
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# XXX avoid manual connect
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udp_sink = self.platform.request("udp_sink")
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self.comb += [
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# control
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udp_port.sink.stb.eq(udp_sink.stb),
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udp_port.sink.sop.eq(udp_sink.sop),
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udp_port.sink.eop.eq(udp_sink.eop),
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udp_sink.ack.eq(udp_port.sink.ack),
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# param
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udp_port.sink.src_port.eq(udp_sink.src_port),
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udp_port.sink.dst_port.eq(udp_sink.dst_port),
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udp_port.sink.ip_address.eq(udp_sink.ip_address),
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udp_port.sink.length.eq(udp_sink.length),
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# payload
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udp_port.sink.data.eq(udp_sink.data),
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udp_port.sink.error.eq(udp_sink.error)
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]
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udp_source = self.platform.request("udp_source")
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self.comb += [
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# control
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udp_source.stb.eq(udp_port.source.stb),
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udp_source.sop.eq(udp_port.source.sop),
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udp_source.eop.eq(udp_port.source.eop),
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udp_port.source.ack.eq(udp_source.ack),
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# param
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udp_source.src_port.eq(udp_port.source.src_port),
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udp_source.dst_port.eq(udp_port.source.dst_port),
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udp_source.ip_address.eq(udp_port.source.ip_address),
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udp_source.length.eq(udp_port.source.length),
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# payload
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udp_source.data.eq(udp_port.source.data),
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udp_source.error.eq(udp_port.source.error)
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]
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# payload
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udp_source.data.eq(udp_port.source.data),
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udp_source.error.eq(udp_port.source.error)
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]
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def main():
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parser = argparse.ArgumentParser(description="LiteEth core builder")
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@ -259,13 +268,15 @@ def main():
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parser.add_argument("--ip_address", default="192.168.0.42", help="IP address")
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args = parser.parse_args()
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soc = Core(phy=args.phy,
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core=args.core,
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clk_freq=100*1000,
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mac_address=args.mac_address,
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ip_address=args.ip_address,
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udp_port=6000,
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**soc_core_argdict(args))
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if args.core == "mac":
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soc = MACCore(phy=args.phy, clk_freq=100*1000000)
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elif args.core == "udp":
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soc = UDPCore(phy=args.phy, clk_freq=100*10000000,
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mac_address=args.mac_address,
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ip_address=args.ip_address,
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port=6000)
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else:
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raise ValueError
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builder = Builder(soc, output_dir="liteeth", compile_gateware=False, csr_csv="liteeth/csr.csv")
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builder.build(build_name="liteeth")
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