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phy/gw5rgmii: avoid synthesis noise by adding missing in/out ports for IODELAY primitives

This commit is contained in:
Gwenhael Goavec-Merou 2024-01-08 07:26:35 +01:00
parent 1c9acfeaa7
commit 1ea28bd93a
1 changed files with 20 additions and 2 deletions
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22
liteeth/phy/gw5rgmii.py
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@ -42,7 +42,11 @@ class LiteEthPHYRGMIITX(LiteXModule):
p_DYN_DLY_EN = "FALSE",
p_ADAPT_EN = "FALSE",
p_C_STATIC_DLY = 0,
i_SDTAP = 0,
i_DLYSTEP = Constant(0, 8),
i_VALUE = 0,
i_DI = tx_ctl_oddrx1f,
o_DF = Open(),
o_DO = pads.tx_ctl,
)
]
@ -58,8 +62,12 @@ class LiteEthPHYRGMIITX(LiteXModule):
p_DYN_DLY_EN = "FALSE",
p_ADAPT_EN = "FALSE",
p_C_STATIC_DLY = 0,
i_DI = tx_data_oddrx1f[i],
o_DO = pads.tx_data[i],
i_SDTAP = 0,
i_DLYSTEP = Constant(0, 8),
i_VALUE = 0,
i_DI = tx_data_oddrx1f[i],
o_DF = Open(),
o_DO = pads.tx_data[i],
)
]
self.comb += sink.ready.eq(1)
@ -85,7 +93,11 @@ class LiteEthPHYRGMIIRX(LiteXModule):
p_DYN_DLY_EN = "FALSE",
p_ADAPT_EN = "FALSE",
p_C_STATIC_DLY = rx_delay_taps,
i_SDTAP = 0,
i_DLYSTEP = Constant(0, 8),
i_VALUE = 0,
i_DI = pads.rx_ctl,
o_DF = Open(),
o_DO = rx_ctl_delayf,
),
DDRInput(
@ -101,7 +113,11 @@ class LiteEthPHYRGMIIRX(LiteXModule):
p_DYN_DLY_EN = "FALSE",
p_ADAPT_EN = "FALSE",
p_C_STATIC_DLY = rx_delay_taps,
i_SDTAP = 0,
i_DLYSTEP = Constant(0, 8),
i_VALUE = 0,
i_DI = pads.rx_data[i],
o_DF = Open(),
o_DO = rx_data_delayf[i]),
DDRInput(
clk = ClockSignal("eth_rx"),
@ -160,6 +176,8 @@ class LiteEthPHYRGMIICRG(LiteXModule):
i_DI = eth_tx_clk_o,
i_DLYSTEP = self._txdelay_taps.storage,
i_SDTAP = 1,
i_VALUE = 0, # FIXME
o_DF = Open(),
o_DO = clock_pads.tx,
)
]