Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #92 from david-sawatzke/dev/small_fixes 

Small mac improvements
This commit is contained in:
enjoy-digital 2021-11-08 10:33:47 +01:00 committed by GitHub
parent 8ba5cf06a6 f520751a69
commit 20e0899109
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 5 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
liteeth/mac/core.py
View File

@ -95,8 +95,8 @@ class LiteEthMACCore(Module, AutoCSR):
self.pipeline.append(tx_preamble) self.pipeline.append(tx_preamble)
def add_gap(self): def add_gap(self):
tx_gap = gap.LiteEthMACGap(datapath_dw) tx_gap = gap.LiteEthMACGap(phy_dw)
tx_gap = ClockDomainsRenamer(cd_tx)(tx_gap) tx_gap = ClockDomainsRenamer("eth_tx")(tx_gap)
self.submodules += tx_gap self.submodules += tx_gap
self.pipeline.append(tx_gap) self.pipeline.append(tx_gap)
@ -117,7 +117,6 @@ class LiteEthMACCore(Module, AutoCSR):
if with_preamble_crc: if with_preamble_crc:
tx_datapath.add_crc() tx_datapath.add_crc()
tx_datapath.add_preamble() tx_datapath.add_preamble()
tx_datapath.add_gap()
if with_sys_datapath: if with_sys_datapath:
# CHECKME: Verify converter/cdc order for the different cases. # CHECKME: Verify converter/cdc order for the different cases.
tx_datapath.add_cdc() tx_datapath.add_cdc()
@ -125,6 +124,8 @@ class LiteEthMACCore(Module, AutoCSR):
tx_datapath.add_converter() tx_datapath.add_converter()
if core_dw != 8: if core_dw != 8:
tx_datapath.add_last_be() tx_datapath.add_last_be()
# Gap insertion has to occurr in phy tx domain to ensure gap is correctly maintained
tx_datapath.add_gap()
tx_datapath.pipeline.append(phy) tx_datapath.pipeline.append(phy)
self.submodules.tx_datapath = tx_datapath self.submodules.tx_datapath = tx_datapath

2
liteeth/mac/crc.py
View File

@ -360,7 +360,7 @@ class LiteEthMACCRCChecker(Module):
# applies to the whole ethernet packet, all the bytes are marked as # applies to the whole ethernet packet, all the bytes are marked as
# containing an error. This way later reducing the data width # containing an error. This way later reducing the data width
# doesn't run into issues with missing the error # doesn't run into issues with missing the error
source.error.eq(sink.error | Replicate(crc.error, dw//8)), source.error.eq(sink.error | Replicate(crc.error & sink.last, dw//8)),
self.error.eq(sink.valid & sink.last & crc.error), self.error.eq(sink.valid & sink.last & crc.error),
If(sink.valid & sink.ready, If(sink.valid & sink.ready,