Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

mac/LiteEthMAC: simplify hybrid mode and avoid some duplication.

This commit is contained in:
Florent Kermarrec 2020-06-19 22:01:22 +02:00
parent 51cd54602b
commit 23b420a2dd
1 changed files with 11 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
liteeth/mac/__init__.py
View File

@ -12,8 +12,8 @@ class LiteEthMAC(Module, AutoCSR):
with_preamble_crc = True, with_preamble_crc = True,
nrxslots = 2, nrxslots = 2,
ntxslots = 2, ntxslots = 2,
cpu_dw = 32,
hw_mac = None): hw_mac = None):
assert interface in ["crossbar", "wishbone", "hybrid"]
self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_preamble_crc) self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_preamble_crc)
self.csrs = [] self.csrs = []
if interface == "crossbar": if interface == "crossbar":
@ -26,29 +26,22 @@ class LiteEthMAC(Module, AutoCSR):
self.core.source.connect(self.depacketizer.sink), self.core.source.connect(self.depacketizer.sink),
self.depacketizer.source.connect(self.crossbar.master.sink) self.depacketizer.source.connect(self.crossbar.master.sink)
] ]
elif interface == "wishbone": else:
self.rx_slots = CSRConstant(nrxslots)
self.tx_slots = CSRConstant(ntxslots)
self.slot_size = CSRConstant(2**bits_for(eth_mtu))
self.submodules.interface = LiteEthMACWishboneInterface(dw, nrxslots, ntxslots, endianness)
self.comb += Port.connect(self.interface, self.core)
self.ev, self.bus = self.interface.sram.ev, self.interface.bus
self.csrs = self.interface.get_csrs() + self.core.get_csrs()
elif interface == "hybrid":
# Wishbone MAC # Wishbone MAC
self.rx_slots = CSRConstant(nrxslots) self.rx_slots = CSRConstant(nrxslots)
self.tx_slots = CSRConstant(ntxslots) self.tx_slots = CSRConstant(ntxslots)
self.slot_size = CSRConstant(2**bits_for(eth_mtu)) self.slot_size = CSRConstant(2**bits_for(eth_mtu))
self.submodules.interface = LiteEthMACWishboneInterface(cpu_dw, nrxslots, ntxslots, endianness) self.submodules.interface = LiteEthMACWishboneInterface(32, nrxslots, ntxslots, endianness)
# HW accelerated MAC
self.submodules.crossbar = LiteEthMACCrossbar(dw)
# MAC crossbar
self.submodules.mac_crossbar = LiteEthMACCoreCrossbar(self.core, self.crossbar, self.interface, dw, cpu_dw, endianness, hw_mac)
# Connections
self.ev, self.bus = self.interface.sram.ev, self.interface.bus self.ev, self.bus = self.interface.sram.ev, self.interface.bus
self.csrs = self.interface.get_csrs() + self.core.get_csrs() self.csrs = self.interface.get_csrs() + self.core.get_csrs()
if interface == "hybrid":
assert dw == 8
# Hardware MAC
self.submodules.crossbar = LiteEthMACCrossbar(dw)
self.submodules.mac_crossbar = LiteEthMACCoreCrossbar(self.core, self.crossbar, self.interface, dw, 32, endianness, hw_mac)
else: else:
raise NotImplementedError assert dw == 32
self.comb += Port.connect(self.interface, self.core)
def get_csrs(self): def get_csrs(self):
return self.csrs return self.csrs