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LiteEthStream2UDPTX: remove extra SyncFIFO

This commit is contained in:
Christoph Mayer 2022-11-04 13:31:15 +01:00
parent 574abece38
commit 251270665f
1 changed files with 22 additions and 34 deletions
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54
liteeth/frontend/stream.py
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@ -28,58 +28,46 @@ class LiteEthStream2UDPTX(Module):
] ]
else: else:
level = Signal(max=fifo_depth+1) level = Signal(max=fifo_depth+1)
counter = Signal(max=fifo_depth+1) counter = Signal(max=fifo_depth+1, reset=1)
# intermediate buffer used to scan for fifo.source.last tags
self.submodules.fifo_buffer = fifo_buffer = stream.SyncFIFO([("data", data_width)], fifo_depth, buffered=True)
# sink FIFO # sink FIFO
self.submodules.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth, buffered=True) self.submodules.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth, buffered=True)
self.comb += sink.connect(fifo.sink)
self.submodules.fsm = fsm = FSM(reset_state="IDLE") # avoid assering FIFO we when the FIFO is full
fsm.act("IDLE", fifo_almost_full = Signal()
# wail until the FIFO is full self.comb += fifo_almost_full.eq(fifo.level >= fifo_depth - 1)
##If((fifo.source.valid & fifo.source.last) | ~fifo.sink.ready,
If(~fifo.sink.ready, # FSM
NextValue(level, fifo.level), self.submodules.fsm = fsm = FSM(reset_state="READ")
NextValue(counter, 1), fsm.act("READ",
NextState("SCAN") If(sink.valid,
) sink.ready.eq(1),
) fifo.sink.data.eq(sink.data),
fsm.act("SCAN", fifo.sink.valid.eq(1), # _we
# copy into fifo_buffer until either a tag is received or there is no data left in the fifo fifo.sink.last.eq(fifo_almost_full | sink.last),
fifo_buffer.sink.data.eq(fifo.source.data),
If( fifo_buffer.sink.ready & fifo.source.valid,
fifo.source.ready.eq(1),
fifo_buffer.sink.valid.eq(1),
fifo_buffer.sink.last.eq((counter == level) | fifo.source.last),
NextValue(counter, counter + 1), NextValue(counter, counter + 1),
If(fifo_buffer.sink.last, If(fifo.sink.last,
# now we know the length of the packet
source.length.eq(counter * (data_width//8)),
NextValue(level, counter), NextValue(level, counter),
NextValue(counter, 1), NextValue(counter, 1),
NextState("SEND") NextState("WRITE")
) )
) )
) )
fsm.act("SEND", fsm.act("WRITE",
# send the data in fifo_buffer
source.valid.eq(1), source.valid.eq(1),
source.last.eq(counter == level), source.last.eq(counter == level),
source.src_port.eq(udp_port), source.src_port.eq(udp_port),
source.dst_port.eq(udp_port), source.dst_port.eq(udp_port),
source.ip_address.eq(ip_address), source.ip_address.eq(ip_address),
source.length.eq(level * (data_width//8)), source.length.eq(level * (data_width//8)),
source.data.eq(fifo_buffer.source.data), source.data.eq(fifo.source.data),
##source.last_be.eq({32:0b1000, 8:0b1}[data_width]),
source.last_be.eq(2**(data_width//8 - 1)), source.last_be.eq(2**(data_width//8 - 1)),
If(source.ready & fifo_buffer.source.valid, If(source.ready & fifo.source.valid,
fifo_buffer.source.ready.eq(1), fifo.source.ready.eq(1),
NextValue(counter, counter + 1), NextValue(counter, counter + 1),
If(source.last, If(source.last,
NextState("IDLE") NextValue(counter, 1),
NextState("READ")
) )
) )
) )