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Merge pull request #85 from lschuermann/dev/mac-wishbone-dw 

liteeth/mac: support SRAM/Wishbone operation with dw > 32 bit
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enjoy-digital 2021-10-23 18:39:54 +02:00 committed by GitHub
parent 9149524623 359b024103
commit 2a5621474c
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1 changed files with 1 additions and 2 deletions
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liteeth/mac/__init__.py
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@ -50,7 +50,7 @@ class LiteEthMAC(Module, AutoCSR):
self.tx_slots = CSRConstant(ntxslots) self.tx_slots = CSRConstant(ntxslots)
self.slot_size = CSRConstant(2**bits_for(eth_mtu)) self.slot_size = CSRConstant(2**bits_for(eth_mtu))
wishbone_interface = LiteEthMACWishboneInterface( wishbone_interface = LiteEthMACWishboneInterface(
dw = 32, dw = dw,
nrxslots = nrxslots, nrxslots = nrxslots,
ntxslots = ntxslots, ntxslots = ntxslots,
endianness = endianness, endianness = endianness,
@ -74,7 +74,6 @@ class LiteEthMAC(Module, AutoCSR):
self.submodules.crossbar = LiteEthMACCrossbar(dw) self.submodules.crossbar = LiteEthMACCrossbar(dw)
self.submodules.mac_crossbar = LiteEthMACCoreCrossbar(self.core, self.crossbar, self.interface, dw, hw_mac) self.submodules.mac_crossbar = LiteEthMACCoreCrossbar(self.core, self.crossbar, self.interface, dw, hw_mac)
else: else:
assert dw == 32
self.comb += self.interface.source.connect(self.core.sink) self.comb += self.interface.source.connect(self.core.sink)
self.comb += self.core.source.connect(self.interface.sink) self.comb += self.core.source.connect(self.interface.sink)