stream/SyncFIFO now exposes fifo level
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@ -238,7 +238,7 @@ class LiteEthMACCRCChecker(Module):
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fifo_full = Signal()
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self.comb += [
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fifo_full.eq(fifo.fifo.level == ratio),
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fifo_full.eq(fifo.level == ratio),
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fifo_in.eq(sink.stb & (~fifo_full | fifo_out)),
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fifo_out.eq(source.stb & source.ack),
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@ -23,7 +23,7 @@ class LiteEthTTYTX(Module):
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level = Signal(max=fifo_depth)
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level_update = Signal()
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self.sync += If(level_update, level.eq(fifo.fifo.level))
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self.sync += If(level_update, level.eq(fifo.level))
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self.submodules.counter = counter = Counter(max=fifo_depth)
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