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mac/crc: Implement 32 bit support in inserter

This commit is contained in:
David Sawatzke 2021-08-08 17:29:55 +02:00
parent 03e847e90b
commit 3f695a8320
1 changed files with 26 additions and 4 deletions
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30
liteeth/mac/crc.py
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@ -144,7 +144,7 @@ class LiteEthMACCRC32(Module):
self.comb += [engines[e].last.eq(regs[-1]) for e in range(dw)] self.comb += [engines[e].last.eq(regs[-1]) for e in range(dw)]
self.comb += [ self.comb += [
If(last_be[e], If(last_be[e],
self.value.eq(~(regs[e][::-1])), self.value.eq(~(engines[e].next[::-1])),
self.error.eq(engines[e].next != self.check)) self.error.eq(engines[e].next != self.check))
for e in range(dw)] for e in range(dw)]
@ -163,9 +163,9 @@ class LiteEthMACCRCInserter(Module):
Attributes Attributes
---------- ----------
sink : in sink : in
Packets octets without CRC. Packet data without CRC.
source : out source : out
Packets octets with CRC. Packet data with CRC.
""" """
def __init__(self, crc_class, description): def __init__(self, crc_class, description):
self.sink = sink = stream.Endpoint(description) self.sink = sink = stream.Endpoint(description)
@ -174,10 +174,15 @@ class LiteEthMACCRCInserter(Module):
# # # # # #
dw = len(sink.data) dw = len(sink.data)
assert dw in [8, 32]
crc = crc_class(dw) crc = crc_class(dw)
fsm = FSM(reset_state="IDLE") fsm = FSM(reset_state="IDLE")
self.submodules += crc, fsm self.submodules += crc, fsm
# crc packet checksum
crc_packet = Signal(crc.width)
last_be = Signal().like(sink.last_be)
fsm.act("IDLE", fsm.act("IDLE",
crc.reset.eq(1), crc.reset.eq(1),
sink.ready.eq(1), sink.ready.eq(1),
@ -189,9 +194,23 @@ class LiteEthMACCRCInserter(Module):
fsm.act("COPY", fsm.act("COPY",
crc.ce.eq(sink.valid & source.ready), crc.ce.eq(sink.valid & source.ready),
crc.data.eq(sink.data), crc.data.eq(sink.data),
crc.last_be.eq(sink.last_be),
sink.connect(source), sink.connect(source),
source.last.eq(0), source.last.eq(0),
source.last_be.eq(0),
If(sink.last,
# Fill the empty space of the last data word with the
# beginning of the crc value
[If(sink.last_be[e],
source.data.eq(Cat(sink.data[:(e+1)*8],
crc.value)[:dw])) for e in range(dw//8)],
).Else(
crc.ce.eq(sink.valid & source.ready),
),
If(sink.valid & sink.last & source.ready, If(sink.valid & sink.last & source.ready,
NextValue(crc_packet, crc.value),
NextValue(last_be, sink.last_be),
NextState("CRC"), NextState("CRC"),
) )
) )
@ -201,7 +220,7 @@ class LiteEthMACCRCInserter(Module):
cnt_done = Signal() cnt_done = Signal()
fsm.act("CRC", fsm.act("CRC",
source.valid.eq(1), source.valid.eq(1),
chooser(crc.value, cnt, source.data, reverse=True), chooser(crc_packet, cnt, source.data, reverse=True),
If(cnt_done, If(cnt_done,
source.last.eq(1), source.last.eq(1),
If(source.ready, NextState("IDLE")) If(source.ready, NextState("IDLE"))
@ -219,6 +238,9 @@ class LiteEthMACCRCInserter(Module):
source.valid.eq(1), source.valid.eq(1),
source.last.eq(1), source.last.eq(1),
source.data.eq(crc.value), source.data.eq(crc.value),
source.last_be.eq(last_be),
[If(last_be[e],
source.data.eq(crc_packet[-(e+1)*8:])) for e in range(dw//8)],
If(source.ready, NextState("IDLE")) If(source.ready, NextState("IDLE"))
) )