phy: use rx_dv instead of dv

liteeth/phy/gmii.py

@@ -32,11 +32,11 @@ class LiteEthPHYGMIIRX(Module):
 
         dv_d = Signal()
         self.sync += [
-            dv_d.eq(pads.dv),
-            source.valid.eq(pads.dv),
+            dv_d.eq(pads.rx_dv),
+            source.valid.eq(pads.rx_dv),
             source.data.eq(pads.rx_data)
         ]
-        self.comb += source.last.eq(~pads.dv & dv_d)
+        self.comb += source.last.eq(~pads.rx_dv & dv_d)
 
 
 class LiteEthPHYGMIICRG(Module, AutoCSR):

liteeth/phy/gmii_mii.py

@@ -17,7 +17,7 @@ modes = {
 }
 
 tx_pads_layout = [("tx_er", 1), ("tx_en", 1), ("tx_data", 8)]
-rx_pads_layout = [("rx_er", 1), ("dv", 1), ("rx_data", 8)]
+rx_pads_layout = [("rx_er", 1), ("rx_dv", 1), ("rx_data", 8)]
 
 
 class LiteEthPHYGMIIMIITX(Module):
@@ -67,10 +67,10 @@ class LiteEthPHYGMIIMIIRX(Module):
         # # #
 
         pads_d = Record(rx_pads_layout)
-        pads_d.dv.reset_less = True
+        pads_d.rx_dv.reset_less = True
         pads_d.rx_data.reset_less = True
         self.sync += [
-            pads_d.dv.eq(pads.dv),
+            pads_d.rx_dv.eq(pads.rx_dv),
             pads_d.rx_data.eq(pads.rx_data)
         ]
 

liteeth/phy/mii.py

@@ -48,12 +48,12 @@ class LiteEthPHYMIIRX(Module):
         self.submodules += converter
 
         self.sync += [
-            converter.reset.eq(~pads.dv),
+            converter.reset.eq(~pads.rx_dv),
             converter.sink.valid.eq(1),
             converter.sink.data.eq(pads.rx_data)
         ]
         self.comb += [
-            converter.sink.last.eq(~pads.dv),
+            converter.sink.last.eq(~pads.rx_dv),
             converter.source.connect(source)
         ]