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mac/core: Move gap into switchable domain & cleanup

This commit is contained in:
David Sawatzke 2021-08-08 21:14:55 +02:00
parent ef214571d5
commit 4119012b84
1 changed files with 11 additions and 11 deletions
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22
liteeth/mac/core.py
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@ -17,31 +17,33 @@ from litex.soc.interconnect.stream import BufferizeEndpoints, DIR_SOURCE, DIR_SI
# MAC Core ----------------------------------------------------------------------------------------- # MAC Core -----------------------------------------------------------------------------------------
class LiteEthMACCore(Module, AutoCSR): class LiteEthMACCore(Module, AutoCSR):
def __init__(self, phy, core_dw, def __init__(self, phy, dw,
endianness = "big", endianness = "big",
with_preamble_crc = True, with_preamble_crc = True,
sys_data_path = True, sys_data_path = True,
with_padding = True): with_padding = True):
core_dw = dw
if core_dw < phy.dw: if core_dw < phy.dw:
raise ValueError("Core data width({}) must be larger than PHY data width({})".format(core_dw, phy.dw)) raise ValueError("Core data width({}) must be larger than PHY data width({})".format(core_dw, phy.dw))
rx_pipeline = [phy] rx_pipeline = [phy]
tx_pipeline = [phy] tx_pipeline = [phy]
cd_tx = "eth_tx" if sys_data_path:
cd_rx = "eth_rx" self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw, endianness)
dw = phy.dw cd_tx = cd_rx = "sys"
dw = core_dw
else:
cd_tx = "eth_tx"
cd_rx = "eth_rx"
dw = phy.dw
# Interpacket gap # Interpacket gap
tx_gap_inserter = gap.LiteEthMACGap(dw) tx_gap_inserter = gap.LiteEthMACGap(dw)
self.submodules += ClockDomainsRenamer(cd_tx)(tx_gap_inserter) self.submodules += ClockDomainsRenamer(cd_tx)(tx_gap_inserter)
tx_pipeline += [tx_gap_inserter] tx_pipeline += [tx_gap_inserter]
if sys_data_path:
self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw, endianness)
cd_tx = cd_rx = "sys"
dw = core_dw
# Preamble / CRC # Preamble / CRC
if isinstance(phy, LiteEthPHYModel): if isinstance(phy, LiteEthPHYModel):
# In simulation, avoid CRC/Preamble to enable direct connection # In simulation, avoid CRC/Preamble to enable direct connection
@ -93,8 +95,6 @@ class LiteEthMACCore(Module, AutoCSR):
if not sys_data_path: if not sys_data_path:
self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw, endianness) self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw, endianness)
cd_tx = cd_rx = "sys"
dw = core_dw
# Graph # Graph
self.submodules.tx_pipeline = stream.Pipeline(*reversed(tx_pipeline)) self.submodules.tx_pipeline = stream.Pipeline(*reversed(tx_pipeline))