Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #94 from enjoy-digital/probe_fifo 

frontend/etherbone: Add 1-Slot PacketFIFO on LiteEthEtherboneProbe to prevent deadlock situation.
This commit is contained in:
enjoy-digital 2021-11-09 11:35:27 +01:00 committed by GitHub
parent 906208e16c 491c5ab150
commit 4dd95ea2a2
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 9 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
liteeth/frontend/etherbone.py
View File

@ -139,14 +139,21 @@ class LiteEthEtherboneProbe(Module):
# # # # # #
self.submodules.fifo = fifo = PacketFIFO(eth_etherbone_packet_user_description(32),
payload_depth = 1,
param_depth = 1,
buffered = False
)
self.comb += sink.connect(fifo.sink)
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
If(sink.valid, If(fifo.source.valid,
NextState("PROBE_RESPONSE") NextState("PROBE_RESPONSE")
) )
) )
fsm.act("PROBE_RESPONSE", fsm.act("PROBE_RESPONSE",
sink.connect(source), fifo.source.connect(source),
source.pf.eq(0), source.pf.eq(0),
source.pr.eq(1), source.pr.eq(1),
If(source.valid & source.ready, If(source.valid & source.ready,