core/mac/sram: simplify last_be code
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@ -28,17 +28,21 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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# length computation
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inc = Signal(3)
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inc_cases = {}
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inc_cases["default"] = inc.eq(4)
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if endianness == "big":
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inc_cases[0b1000] = inc.eq(1)
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inc_cases[0b0100] = inc.eq(2)
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inc_cases[0b0010] = inc.eq(3)
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self.comb += Case(sink.last_be, {
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0b1000 : inc.eq(1),
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0b0100 : inc.eq(2),
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0b0010 : inc.eq(3),
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"default" : inc.eq(4)
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})
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else:
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inc_cases[0b0001] = inc.eq(1)
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inc_cases[0b0010] = inc.eq(2)
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inc_cases[0b0100] = inc.eq(3)
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self.comb += Case(sink.last_be, inc_cases)
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self.comb += Case(sink.last_be, {
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0b0001 : inc.eq(1),
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0b0010 : inc.eq(2),
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0b0100 : inc.eq(3),
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"default" : inc.eq(4)
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})
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counter = Signal(lengthbits)
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counter_reset = Signal()
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@ -206,18 +210,22 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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)
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length_lsb = fifo.source.length[0:2]
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length_cases = {}
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if endianness == "big":
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length_cases[0] = source.last_be.eq(0b0001)
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length_cases[1] = source.last_be.eq(0b1000)
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length_cases[2] = source.last_be.eq(0b0100)
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length_cases[3] = source.last_be.eq(0b0010)
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self.comb += If(last,
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Case(length_lsb, {
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0 : source.last.be.eq(0b0001),
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1 : source.last.be.eq(0b1000),
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2 : source.last.be.eq(0b0100),
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3 : source.last_be.eq(0b0010)
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}))
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else:
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length_cases[0] = source.last_be.eq(0b1000)
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length_cases[1] = source.last_be.eq(0b0001)
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length_cases[2] = source.last_be.eq(0b0010)
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length_cases[3] = source.last_be.eq(0b0100)
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self.comb += If(last, Case(length_lsb, length_cases))
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self.comb += If(last,
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Case(length_lsb, {
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0 : source.last.be.eq(0b1000),
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1 : source.last.be.eq(0b0001),
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2 : source.last.be.eq(0b0010),
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3 : source.last_be.eq(0b0100)
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}))
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fsm.act("SEND",
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source.valid.eq(1),
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