[init] 10BASE-T implementation
This commit is contained in:
Charles-Henri Mousset
parent
694cc81d77
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526761a4d9
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2018 David Shah <dave@ds0.me>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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import sys
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from migen import *
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from litex_boards.platforms import ulx3s
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from litex_boards.targets.ulx3s import _CRG
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.gpio import GPIOOut
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from litedram import modules as litedram_modules
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litex.build.generic_platform import *
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from liteeth.phy import LiteEthPHYETHERNET
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# IOs ----------------------------------------------------------------------------------------------
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_eth_io = [
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# Direct connect 10BASE-T, full-duplex Ethernet
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("eth", 0,
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Subsignal("td_p", Pins("A2")), # J1 GP9 - Green/White
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Subsignal("td_n", Pins("B1")), # J1 GN9 - Green
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Subsignal("rd_p", Pins("C4"), IOStandard("LVDS"), Misc("DIFFRESISTOR=100")), # J1 GP10 - Orange/White
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Subsignal("rd_n", Pins("B4")), # J1 GN10 - Orange
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IOStandard("LVCMOS33"),
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),
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]
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis",
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sys_clk_freq=int(40e6), **kwargs):
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platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain)
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platform.add_extension(_eth_io)
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# SoCCore ----------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, sys_clk_freq,
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ident = "LiteEth bench on ULX3S",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Etherbone --------------------------------------------------------------------------------
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self.submodules.ethphy = LiteEthPHYETHERNET(
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pads = self.platform.request("eth"),
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refclk_cd = "sys",
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with_hw_init_reset = False)
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self.add_csr("ethphy")
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self.add_etherbone(phy=self.ethphy, buffer_depth=255)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
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parser.add_argument("--device", default="LFE5U-45F", help="FPGA device: LFE5U-12F, LFE5U-25F, LFE5U-45F (default) or LFE5U-85F")
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parser.add_argument("--revision", default="2.0", help="Board revision: 2.0 (default) or 1.7")
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parser.add_argument("--sys-clk-freq", default=40e6, help="System clock frequency (default: 50MHz)")
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builder_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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soc = BenchSoC(
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device = args.device,
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revision = args.revision,
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toolchain = args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)))
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder.build(**builder_kargs, run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + (".svf" if args.toolchain == "trellis" else ".bit")))
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if __name__ == "__main__":
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main()
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@ -26,6 +26,7 @@ from liteeth.phy.mii import LiteEthPHYMII
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from liteeth.phy.rmii import LiteEthPHYRMII
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from liteeth.phy.gmii import LiteEthPHYGMII
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from liteeth.phy.gmii_mii import LiteEthPHYGMIIMII
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from liteeth.phy.ethernet import LiteEthPHYETHERNET
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from liteeth.phy.s6rgmii import LiteEthPHYRGMII as LiteEthS6PHYRGMII
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from liteeth.phy.s7rgmii import LiteEthPHYRGMII as LiteEthS7PHYRGMII
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@ -0,0 +1,220 @@
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2021 Charles-Henri Mousset <ch.mousset@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DDROutput
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from liteeth.common import *
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from liteeth.phy.common import *
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from litex.build.io import DifferentialInput
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from litex.soc.integration.doc import AutoDoc, ModuleDoc
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def converter_description(dw):
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payload_layout = [("data", dw)]
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return EndpointDescription(payload_layout)
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class LiteEthPHYETHERNETTX(Module):
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def __init__(self, pads):
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self.sink = sink = stream.Endpoint(eth_phy_description(8))
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self.submodules.fsm = fsm = FSM("IDLE")
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# # #
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# deserializing
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converter = stream.StrideConverter(converter_description(8),
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converter_description(1))
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self.submodules += converter
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self.comb += [
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converter.sink.valid.eq(sink.valid),
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converter.sink.data.eq(sink.data),
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sink.ready.eq(converter.sink.ready),
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converter.source.ready.eq(fsm.ongoing("TX"))
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]
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# Manchester encoding
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tx_bit = Signal()
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tx_cnt = Signal(2)
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tx_bit_strb = Signal()
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tx = Signal(reset_less=True)
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txe = Signal(reset_less=True)
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self.comb += tx_bit_strb.eq(tx_cnt == 0b11)
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self.sync += [tx_cnt.eq(tx_cnt+1)]
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# Output logic
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if hasattr(pads, "tx") and hasattr(pads, "tx_en"): # RS485 half duplex mode
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self.comb += [pads.tx.eq(tx), pads.txe.eq(txe)]
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else: # A true differential output buffer is not necessary at 20Mbps(manchester)
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self.comb += [pads.td_p.eq(tx & txe), pads.td_n.eq(~tx & txe)]
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# Normal Link Pulse generation timer
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NLP_PERIOD = int(40e6/1000*16)
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nlp_timeout = Signal()
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nlp_counter = Signal(max=NLP_PERIOD+1)
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self.comb += [
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nlp_timeout.eq(nlp_counter == NLP_PERIOD-1),
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]
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self.sync += [
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If(nlp_timeout,
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nlp_counter.eq(0),
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).Else(
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nlp_counter.eq(nlp_counter+1),
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),
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]
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# Main FSM
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fsm.act("IDLE",
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# send the Normal Link Pulses
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If(nlp_timeout & (tx_bit_strb),
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NextState("NLP1"),
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),
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converter.sink.ready.eq(tx_bit_strb),
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If(converter.sink.valid & converter.sink.ready,
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NextState("TX"),
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NextValue(tx_bit, converter.sink.data),
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),
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)
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fsm.act("NLP1",
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# we emit a '1' for 1 bit time
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tx.eq(1),
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txe.eq(1),
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If(tx_bit_strb,
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NextState("NLP2"),
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)
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)
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fsm.act("NLP2",
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# we emit a '0' for 1 bit time
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tx.eq(0),
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txe.eq(1),
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If(tx_bit_strb,
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NextState("IDLE"),
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)
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)
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fsm.act("TX",
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tx.eq(tx_bit ^ tx_cnt[1]),
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txe.eq(converter.sink.valid), # should stay at 1
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If(tx_bit_strb,
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converter.sink.ready.eq(1),
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NextValue(tx_bit, converter.sink.data),
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),
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If(sink.last_be,
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NextState("IDLE"),
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)
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)
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class LiteEthPHYETHERNETRX(Module):
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def __init__(self, pads):
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self.source = source = stream.Endpoint(eth_phy_description(8))
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# # #
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# Single Ended / Differential input
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rx = Signal()
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if not hasattr(pads, "rx"):
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self.specials += DifferentialInput(pads.rd_p, pads.rd_n, rx)
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else:
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self.comb += rx.eq(pads.rx)
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# Manchester input
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mc_in_data = Signal(3)
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mc_cnt = Signal(2)
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bit_valid = Signal()
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bit_value = Signal()
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self.comb += [
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bit_valid.eq((mc_in_data[2] ^ mc_in_data[1]) & (mc_cnt == 0b00)),
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bit_value.eq(mc_in_data[2]),
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]
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self.sync += [
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mc_in_data.eq(Cat(rx, mc_in_data[0:1])),
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If(bit_valid,
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mc_cnt.eq(3),
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).Elif(mc_cnt,
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mc_cnt.eq(mc_cnt-1),
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),
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]
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# Receive timeout / NLP and noise filter
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timeout_cnt = Signal(3)
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timeout = Signal()
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self.comb += [
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timeout.eq(timeout_cnt == 0),
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]
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self.sync += [
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If(bit_valid,
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timeout_cnt.eq(0b111),
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).Elif(timeout_cnt,
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timeout_cnt.eq(timeout_cnt - 1),
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)
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]
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# bit to byte logic
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bit_cnt = Signal(3)
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byte = Signal(8)
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self.sync += [
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If(timeout,
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bit_cnt.eq(0),
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).Elif(bit_valid,
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bit_cnt.eq(bit_cnt+1),
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byte.eq(Cat(byte[1:], bit_value)),
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),
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]
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self.comb += [
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self.source.valid.eq((bit_cnt == 7) & bit_valid),
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self.source.data.eq(byte),
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]
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class LiteEthPHYETHERNETCRG(Module, AutoCSR):
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def __init__(self, refclk_cd, with_hw_init_reset):
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self._reset = CSRStorage()
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# # #
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# RX/TX clocks
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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# This is entirely clocked internally
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assert refclk_cd
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self.comb += self.cd_eth_rx.clk.eq(ClockSignal(refclk_cd))
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self.comb += self.cd_eth_tx.clk.eq(ClockSignal(refclk_cd))
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# Reset
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self.reset = reset = Signal()
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if with_hw_init_reset:
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self.submodules.hw_reset = LiteEthPHYHWReset()
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self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
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else:
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self.comb += reset.eq(self._reset.storage)
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self.specials += [
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AsyncResetSynchronizer(self.cd_eth_tx, reset),
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AsyncResetSynchronizer(self.cd_eth_rx, reset),
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]
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class LiteEthPHYETHERNET(Module, AutoCSR, ModuleDoc):
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"""
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Direct connection to a 10Base-T network, using only series capacitors with FPGIO IOs.
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This probably violates some parts of the IEEE802.3 standard. Use at your own risk!
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"""
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dw = 8
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tx_clk_freq = 40e6
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rx_clk_freq = 40e6
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def __init__(self, pads, refclk_cd="eth", with_hw_init_reset=True):
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self.submodules.crg = LiteEthPHYETHERNETCRG(refclk_cd, with_hw_init_reset)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYETHERNETTX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYETHERNETRX(pads))
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self.sink, self.source = self.tx.sink, self.rx.source
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