mac/core: Split add_converter in add_cdc/add_converter/add_last_be.
This commit is contained in:
Florent Kermarrec
parent
a4a070af4d
commit
5276a7543f
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@ -52,31 +52,27 @@ class LiteEthMACCore(Module, AutoCSR):
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def __init__(self):
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self.pipeline = []
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def add_cdc(self):
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tx_cdc = stream.ClockDomainCrossing(eth_phy_description(core_dw),
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cd_from = "sys",
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cd_to = "eth_tx",
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depth = 32)
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self.submodules += tx_cdc
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self.pipeline.append(tx_cdc)
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def add_converter(self):
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# CHECKME: Order probably needs to be adapted based on core_dw/phy_dw ratio.
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# Cross Domain Crossing.
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tx_cdc = stream.ClockDomainCrossing(eth_phy_description(core_dw),
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cd_from = "sys",
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cd_to = "eth_tx",
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depth = 32)
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self.submodules += tx_cdc
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self.pipeline.append(tx_cdc)
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tx_converter = stream.StrideConverter(
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description_from = eth_phy_description(core_dw),
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description_to = eth_phy_description(phy_dw))
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tx_converter = ClockDomainsRenamer("eth_tx")(tx_converter)
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self.submodules += tx_converter
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self.pipeline.append(tx_converter)
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# Converters.
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if core_dw != phy_dw:
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tx_converter = stream.StrideConverter(
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description_from = eth_phy_description(core_dw),
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description_to = eth_phy_description(phy_dw))
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tx_converter = ClockDomainsRenamer("eth_tx")(tx_converter)
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self.submodules += tx_converter
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self.pipeline.append(tx_converter)
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# Delimiters.
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if core_dw != 8:
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tx_last_be = last_be.LiteEthMACTXLastBE(phy_dw)
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tx_last_be = ClockDomainsRenamer("eth_tx")(tx_last_be)
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self.submodules += tx_last_be
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self.pipeline.append(tx_last_be)
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def add_last_be(self):
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tx_last_be = last_be.LiteEthMACTXLastBE(phy_dw)
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tx_last_be = ClockDomainsRenamer("eth_tx")(tx_last_be)
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self.submodules += tx_last_be
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self.pipeline.append(tx_last_be)
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def add_padding(self):
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tx_padding = padding.LiteEthMACPaddingInserter(datapath_dw, (eth_min_frame_length - eth_fcs_length))
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@ -109,7 +105,12 @@ class LiteEthMACCore(Module, AutoCSR):
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tx_datapath = TXDatapath()
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tx_datapath.pipeline.append(self.sink)
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if not with_sys_datapath:
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tx_datapath.add_converter()
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# CHECKME: Verify converter/cdc order for the different cases.
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tx_datapath.add_cdc()
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if core_dw != phy_dw:
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tx_datapath.add_converter()
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if core_dw != 8:
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tx_datapath.add_last_be()
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if with_padding:
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tx_datapath.add_padding()
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if with_preamble_crc:
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@ -117,7 +118,12 @@ class LiteEthMACCore(Module, AutoCSR):
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tx_datapath.add_preamble()
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tx_datapath.add_gap()
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if with_sys_datapath:
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tx_datapath.add_converter()
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# CHECKME: Verify converter/cdc order for the different cases.
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tx_datapath.add_cdc()
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if core_dw != phy_dw:
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tx_datapath.add_converter()
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if core_dw != 8:
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tx_datapath.add_last_be()
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tx_datapath.pipeline.append(phy)
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self.submodules.tx_datapath = tx_datapath
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@ -159,25 +165,21 @@ class LiteEthMACCore(Module, AutoCSR):
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self.submodules += rx_padding
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self.pipeline.append(rx_padding)
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def add_last_be(self):
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rx_last_be = last_be.LiteEthMACRXLastBE(phy_dw)
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rx_last_be = ClockDomainsRenamer("eth_rx")(rx_last_be)
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self.submodules += rx_last_be
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self.pipeline.append(rx_last_be)
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def add_converter(self):
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# CHECKME: Order probably needs to be adapted based on core_dw/phy_dw ratio.
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# Delimiters.
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if core_dw != 8:
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rx_last_be = last_be.LiteEthMACRXLastBE(phy_dw)
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rx_last_be = ClockDomainsRenamer("eth_rx")(rx_last_be)
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self.submodules += rx_last_be
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self.pipeline.append(rx_last_be)
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rx_converter = stream.StrideConverter(
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description_from = eth_phy_description(phy_dw),
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description_to = eth_phy_description(core_dw))
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rx_converter = ClockDomainsRenamer("eth_rx")(rx_converter)
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self.submodules += rx_converter
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self.pipeline.append(rx_converter)
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# Converters.
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if core_dw != phy_dw:
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rx_converter = stream.StrideConverter(
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description_from = eth_phy_description(phy_dw),
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description_to = eth_phy_description(core_dw))
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rx_converter = ClockDomainsRenamer("eth_rx")(rx_converter)
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self.submodules += rx_converter
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self.pipeline.append(rx_converter)
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# Cross Domain Crossing
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def add_cdc(self):
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rx_cdc = stream.ClockDomainCrossing(eth_phy_description(core_dw),
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cd_from = "eth_rx",
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cd_to = "sys",
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@ -191,13 +193,23 @@ class LiteEthMACCore(Module, AutoCSR):
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rx_datapath = RXDatapath()
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rx_datapath.pipeline.append(phy)
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if with_sys_datapath:
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rx_datapath.add_converter()
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if core_dw != 8:
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rx_datapath.add_last_be()
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# CHECKME: Verify converter/cdc order for the different cases.
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if core_dw != phy_dw:
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rx_datapath.add_converter()
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rx_datapath.add_cdc()
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if with_preamble_crc:
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rx_datapath.add_preamble()
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rx_datapath.add_crc()
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if with_padding:
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rx_datapath.add_padding()
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if not with_sys_datapath:
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rx_datapath.add_converter()
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if core_dw != 8:
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rx_datapath.add_last_be()
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# CHECKME: Verify converter/cdc order for the different cases.
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if core_dw != phy_dw:
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rx_datapath.add_converter()
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rx_datapath.add_cdc()
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rx_datapath.pipeline.append(self.source)
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self.submodules.rx_datapath = rx_datapath
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