mirror of
https://github.com/enjoy-digital/liteeth.git
synced 2025-01-03 03:43:37 -05:00
global: pass data_width(dw) parameter to modules to prepare for 10Gbps/25Gbps links
To support 10Gbps/25Gbps, the hardware stack will need to handle multiple bytes/clock cycle. Pass dw to all modules to allow making use of it in the future. For now dw=8.
This commit is contained in:
Vamsi K Vytla
Florent Kermarrec
parent
ba83253ffa
commit
57be29e68a
8 changed files with 113 additions and 111 deletions
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@ -6,19 +6,20 @@ from liteeth.core.udp import LiteEthUDP
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from liteeth.core.icmp import LiteEthICMP
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class LiteEthIPCore(Module, AutoCSR):
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def __init__(self, phy, mac_address, ip_address, clk_freq, with_icmp=True):
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def __init__(self, phy, mac_address, ip_address, clk_freq, with_icmp=True, dw=8):
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if isinstance(ip_address, str):
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ip_address = convert_ip(ip_address)
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self.submodules.mac = LiteEthMAC(phy, 8, interface="crossbar", with_preamble_crc=True)
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self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address, clk_freq)
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self.submodules.ip = LiteEthIP(self.mac, mac_address, ip_address, self.arp.table)
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self.submodules.mac = LiteEthMAC(phy, dw, interface="crossbar", with_preamble_crc=True)
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self.submodules.arp = LiteEthARP(self.mac, mac_address, ip_address, clk_freq, dw=dw)
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self.submodules.ip = LiteEthIP(self.mac, mac_address, ip_address, self.arp.table, dw=dw)
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if with_icmp:
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self.submodules.icmp = LiteEthICMP(self.ip, ip_address)
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self.submodules.icmp = LiteEthICMP(self.ip, ip_address, dw=dw)
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class LiteEthUDPIPCore(LiteEthIPCore):
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def __init__(self, phy, mac_address, ip_address, clk_freq, with_icmp=True):
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def __init__(self, phy, mac_address, ip_address, clk_freq, with_icmp=True, dw=8):
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if isinstance(ip_address, str):
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ip_address = convert_ip(ip_address)
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LiteEthIPCore.__init__(self, phy, mac_address, ip_address, clk_freq, with_icmp)
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self.submodules.udp = LiteEthUDP(self.ip, ip_address)
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LiteEthIPCore.__init__(self, phy, mac_address, ip_address, clk_freq, dw=dw,
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with_icmp=with_icmp)
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self.submodules.udp = LiteEthUDP(self.ip, ip_address, dw=dw)
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@ -18,21 +18,21 @@ _arp_table_layout = [
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# arp tx
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class LiteEthARPPacketizer(Packetizer):
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def __init__(self):
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def __init__(self, dw=8):
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Packetizer.__init__(self,
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eth_arp_description(8),
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eth_mac_description(8),
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eth_arp_description(dw),
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eth_mac_description(dw),
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arp_header)
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class LiteEthARPTX(Module):
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def __init__(self, mac_address, ip_address):
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def __init__(self, mac_address, ip_address, dw=8):
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self.sink = sink = stream.Endpoint(_arp_table_layout)
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self.source = source = stream.Endpoint(eth_mac_description(8))
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self.source = source = stream.Endpoint(eth_mac_description(dw))
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# # #
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self.submodules.packetizer = packetizer = LiteEthARPPacketizer()
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self.submodules.packetizer = packetizer = LiteEthARPPacketizer(dw)
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counter = Signal(max=max(arp_header.length, eth_min_len), reset_less=True)
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counter_reset = Signal()
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@ -89,21 +89,21 @@ class LiteEthARPTX(Module):
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# arp rx
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class LiteEthARPDepacketizer(Depacketizer):
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def __init__(self):
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def __init__(self, dw=8):
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Depacketizer.__init__(self,
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eth_mac_description(8),
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eth_arp_description(8),
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eth_mac_description(dw),
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eth_arp_description(dw),
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arp_header)
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class LiteEthARPRX(Module):
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def __init__(self, mac_address, ip_address):
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self.sink = sink = stream.Endpoint(eth_mac_description(8))
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def __init__(self, mac_address, ip_address, dw=8):
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self.sink = sink = stream.Endpoint(eth_mac_description(dw))
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self.source = source = stream.Endpoint(_arp_table_layout)
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# # #
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self.submodules.depacketizer = depacketizer = LiteEthARPDepacketizer()
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self.submodules.depacketizer = depacketizer = LiteEthARPDepacketizer(dw)
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self.comb += sink.connect(depacketizer.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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@ -291,15 +291,15 @@ class LiteEthARPTable(Module):
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# arp
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class LiteEthARP(Module):
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def __init__(self, mac, mac_address, ip_address, clk_freq):
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self.submodules.tx = tx = LiteEthARPTX(mac_address, ip_address)
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self.submodules.rx = rx = LiteEthARPRX(mac_address, ip_address)
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def __init__(self, mac, mac_address, ip_address, clk_freq, dw=8):
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self.submodules.tx = tx = LiteEthARPTX(mac_address, ip_address, dw)
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self.submodules.rx = rx = LiteEthARPRX(mac_address, ip_address, dw)
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self.submodules.table = table = LiteEthARPTable(clk_freq)
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self.comb += [
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rx.source.connect(table.sink),
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table.source.connect(tx.sink)
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]
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mac_port = mac.crossbar.get_port(ethernet_type_arp)
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mac_port = mac.crossbar.get_port(ethernet_type_arp, dw=dw)
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self.comb += [
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tx.source.connect(mac_port.sink),
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mac_port.source.connect(rx.sink)
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@ -9,21 +9,21 @@ from litex.soc.interconnect.packet import Depacketizer, Packetizer
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# icmp tx
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class LiteEthICMPPacketizer(Packetizer):
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def __init__(self):
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def __init__(self, dw=8):
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Packetizer.__init__(self,
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eth_icmp_description(8),
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eth_ipv4_user_description(8),
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eth_icmp_description(dw),
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eth_ipv4_user_description(dw),
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icmp_header)
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class LiteEthICMPTX(Module):
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def __init__(self, ip_address):
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self.sink = sink = stream.Endpoint(eth_icmp_user_description(8))
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self.source = source = stream.Endpoint(eth_ipv4_user_description(8))
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def __init__(self, ip_address, dw=8):
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self.sink = sink = stream.Endpoint(eth_icmp_user_description(dw))
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self.source = source = stream.Endpoint(eth_ipv4_user_description(dw))
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# # #
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self.submodules.packetizer = packetizer = LiteEthICMPPacketizer()
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self.submodules.packetizer = packetizer = LiteEthICMPPacketizer(dw)
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self.comb += [
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packetizer.sink.valid.eq(sink.valid),
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packetizer.sink.last.eq(sink.last),
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@ -56,21 +56,21 @@ class LiteEthICMPTX(Module):
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# icmp rx
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class LiteEthICMPDepacketizer(Depacketizer):
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def __init__(self):
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def __init__(self, dw=8):
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Depacketizer.__init__(self,
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eth_ipv4_user_description(8),
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eth_icmp_description(8),
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eth_ipv4_user_description(dw),
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eth_icmp_description(dw),
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icmp_header)
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class LiteEthICMPRX(Module):
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def __init__(self, ip_address):
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self.sink = sink = stream.Endpoint(eth_ipv4_user_description(8))
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self.source = source = stream.Endpoint(eth_icmp_user_description(8))
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def __init__(self, ip_address, dw=8):
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self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw))
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self.source = source = stream.Endpoint(eth_icmp_user_description(dw))
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# # #
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self.submodules.depacketizer = depacketizer = LiteEthICMPDepacketizer()
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self.submodules.depacketizer = depacketizer = LiteEthICMPDepacketizer(dw)
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self.comb += sink.connect(depacketizer.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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@ -123,14 +123,14 @@ class LiteEthICMPRX(Module):
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# icmp echo
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class LiteEthICMPEcho(Module):
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def __init__(self):
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self.sink = sink = stream.Endpoint(eth_icmp_user_description(8))
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self.source = source = stream.Endpoint(eth_icmp_user_description(8))
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def __init__(self, dw=8):
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self.sink = sink = stream.Endpoint(eth_icmp_user_description(dw))
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self.source = source = stream.Endpoint(eth_icmp_user_description(dw))
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# # #
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# TODO: optimize ressources (no need to store parameters as datas)
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self.submodules.buffer = stream.SyncFIFO(eth_icmp_user_description(8), 128, buffered=True)
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self.submodules.buffer = stream.SyncFIFO(eth_icmp_user_description(dw), 128//(dw//8), buffered=True)
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self.comb += [
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sink.connect(self.buffer.sink),
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self.buffer.source.connect(source),
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@ -141,15 +141,15 @@ class LiteEthICMPEcho(Module):
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# icmp
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class LiteEthICMP(Module):
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def __init__(self, ip, ip_address):
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self.submodules.tx = tx = LiteEthICMPTX(ip_address)
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self.submodules.rx = rx = LiteEthICMPRX(ip_address)
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self.submodules.echo = echo = LiteEthICMPEcho()
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def __init__(self, ip, ip_address, dw=8):
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self.submodules.tx = tx = LiteEthICMPTX(ip_address, dw)
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self.submodules.rx = rx = LiteEthICMPRX(ip_address, dw)
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self.submodules.echo = echo = LiteEthICMPEcho(dw)
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self.comb += [
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rx.source.connect(echo.sink),
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echo.source.connect(tx.sink)
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]
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ip_port = ip.crossbar.get_port(icmp_protocol)
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ip_port = ip.crossbar.get_port(icmp_protocol, dw)
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self.comb += [
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tx.source.connect(ip_port.sink),
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ip_port.source.connect(rx.sink)
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@ -29,13 +29,13 @@ class LiteEthIPV4UserPort(LiteEthIPV4SlavePort):
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class LiteEthIPV4Crossbar(LiteEthCrossbar):
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def __init__(self):
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LiteEthCrossbar.__init__(self, LiteEthIPV4MasterPort, "protocol")
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def __init__(self, dw=8):
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LiteEthCrossbar.__init__(self, LiteEthIPV4MasterPort, "protocol", dw)
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def get_port(self, protocol):
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def get_port(self, protocol, dw=8):
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if protocol in self.users.keys():
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raise ValueError("Protocol {0:#x} already assigned".format(protocol))
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port = LiteEthIPV4UserPort(8)
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port = LiteEthIPV4UserPort(dw)
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self.users[protocol] = port
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return port
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@ -84,17 +84,17 @@ class LiteEthIPV4Checksum(Module):
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# ip tx
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class LiteEthIPV4Packetizer(Packetizer):
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def __init__(self):
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def __init__(self, dw=8):
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Packetizer.__init__(self,
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eth_ipv4_description(8),
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eth_mac_description(8),
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eth_ipv4_description(dw),
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eth_mac_description(dw),
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ipv4_header)
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class LiteEthIPTX(Module):
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def __init__(self, mac_address, ip_address, arp_table):
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self.sink = sink = stream.Endpoint(eth_ipv4_user_description(8))
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self.source = source = stream.Endpoint(eth_mac_description(8))
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def __init__(self, mac_address, ip_address, arp_table, dw=8):
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self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw))
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self.source = source = stream.Endpoint(eth_mac_description(dw))
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self.target_unreachable = Signal()
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# # #
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@ -105,7 +105,7 @@ class LiteEthIPTX(Module):
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checksum.reset.eq(source.valid & source.last & source.ready)
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]
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self.submodules.packetizer = packetizer = LiteEthIPV4Packetizer()
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self.submodules.packetizer = packetizer = LiteEthIPV4Packetizer(dw)
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self.comb += [
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packetizer.sink.valid.eq(sink.valid & checksum.done),
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packetizer.sink.last.eq(sink.last),
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@ -176,21 +176,21 @@ class LiteEthIPTX(Module):
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# ip rx
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class LiteEthIPV4Depacketizer(Depacketizer):
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def __init__(self):
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def __init__(self, dw=8):
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Depacketizer.__init__(self,
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eth_mac_description(8),
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eth_ipv4_description(8),
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eth_mac_description(dw),
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eth_ipv4_description(dw),
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ipv4_header)
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class LiteEthIPRX(Module):
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def __init__(self, mac_address, ip_address):
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self.sink = sink = stream.Endpoint(eth_mac_description(8))
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self.source = source = stream.Endpoint(eth_ipv4_user_description(8))
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def __init__(self, mac_address, ip_address, dw=8):
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self.sink = sink = stream.Endpoint(eth_mac_description(dw))
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self.source = source = stream.Endpoint(eth_ipv4_user_description(dw))
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# # #
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self.submodules.depacketizer = depacketizer = LiteEthIPV4Depacketizer()
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self.submodules.depacketizer = depacketizer = LiteEthIPV4Depacketizer(dw)
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self.comb += sink.connect(depacketizer.sink)
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self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=False)
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@ -253,15 +253,15 @@ class LiteEthIPRX(Module):
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# ip
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class LiteEthIP(Module):
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def __init__(self, mac, mac_address, ip_address, arp_table):
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self.submodules.tx = tx = LiteEthIPTX(mac_address, ip_address, arp_table)
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self.submodules.rx = rx = LiteEthIPRX(mac_address, ip_address)
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mac_port = mac.crossbar.get_port(ethernet_type_ip)
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def __init__(self, mac, mac_address, ip_address, arp_table, dw=8):
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self.submodules.tx = tx = LiteEthIPTX(mac_address, ip_address, arp_table, dw=dw)
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self.submodules.rx = rx = LiteEthIPRX(mac_address, ip_address, dw=dw)
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mac_port = mac.crossbar.get_port(ethernet_type_ip, dw)
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self.comb += [
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tx.source.connect(mac_port.sink),
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mac_port.source.connect(rx.sink)
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]
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self.submodules.crossbar = crossbar = LiteEthIPV4Crossbar()
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self.submodules.crossbar = crossbar = LiteEthIPV4Crossbar(dw)
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self.comb += [
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crossbar.master.source.connect(tx.sink),
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rx.source.connect(crossbar.master.sink)
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@ -30,15 +30,16 @@ class LiteEthUDPUserPort(LiteEthUDPSlavePort):
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class LiteEthUDPCrossbar(LiteEthCrossbar):
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def __init__(self):
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LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port")
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def __init__(self, dw=8):
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self.dw = dw
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LiteEthCrossbar.__init__(self, LiteEthUDPMasterPort, "dst_port", dw=dw)
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def get_port(self, udp_port, dw=8, cd="sys"):
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if udp_port in self.users.keys():
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raise ValueError("Port {0:#x} already assigned".format(udp_port))
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user_port = LiteEthUDPUserPort(dw)
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internal_port = LiteEthUDPUserPort(8)
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internal_port = LiteEthUDPUserPort(self.dw)
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# tx
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tx_stream = user_port.sink
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@ -48,9 +49,9 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
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self.submodules += tx_cdc
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self.comb += tx_stream.connect(tx_cdc.sink)
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tx_stream = tx_cdc.source
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if dw != 8:
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if dw != self.dw:
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tx_converter = stream.StrideConverter(eth_udp_user_description(user_port.dw),
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eth_udp_user_description(8))
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eth_udp_user_description(self.dw))
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self.submodules += tx_converter
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self.comb += tx_stream.connect(tx_converter.sink)
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tx_stream = tx_converter.source
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@ -58,8 +59,8 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
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# rx
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rx_stream = internal_port.source
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if dw != 8:
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rx_converter = stream.StrideConverter(eth_udp_user_description(8),
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if dw != self.dw:
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rx_converter = stream.StrideConverter(eth_udp_user_description(self.dw),
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eth_udp_user_description(user_port.dw))
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self.submodules += rx_converter
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self.comb += rx_stream.connect(rx_converter.sink)
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@ -79,21 +80,21 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
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# udp tx
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class LiteEthUDPPacketizer(Packetizer):
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def __init__(self):
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def __init__(self, dw=8):
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Packetizer.__init__(self,
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eth_udp_description(8),
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eth_ipv4_user_description(8),
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eth_udp_description(dw),
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eth_ipv4_user_description(dw),
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udp_header)
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class LiteEthUDPTX(Module):
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def __init__(self, ip_address):
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self.sink = sink = stream.Endpoint(eth_udp_user_description(8))
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self.source = source = stream.Endpoint(eth_ipv4_user_description(8))
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def __init__(self, ip_address, dw=8):
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self.sink = sink = stream.Endpoint(eth_udp_user_description(dw))
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self.source = source = stream.Endpoint(eth_ipv4_user_description(dw))
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# # #
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self.submodules.packetizer = packetizer = LiteEthUDPPacketizer()
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self.submodules.packetizer = packetizer = LiteEthUDPPacketizer(dw=dw)
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self.comb += [
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packetizer.sink.valid.eq(sink.valid),
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packetizer.sink.last.eq(sink.last),
|
||||
|
|
@ -126,21 +127,21 @@ class LiteEthUDPTX(Module):
|
|||
# udp rx
|
||||
|
||||
class LiteEthUDPDepacketizer(Depacketizer):
|
||||
def __init__(self):
|
||||
def __init__(self, dw=8):
|
||||
Depacketizer.__init__(self,
|
||||
eth_ipv4_user_description(8),
|
||||
eth_udp_description(8),
|
||||
eth_ipv4_user_description(dw),
|
||||
eth_udp_description(dw),
|
||||
udp_header)
|
||||
|
||||
|
||||
class LiteEthUDPRX(Module):
|
||||
def __init__(self, ip_address):
|
||||
self.sink = sink = stream.Endpoint(eth_ipv4_user_description(8))
|
||||
self.source = source = stream.Endpoint(eth_udp_user_description(8))
|
||||
def __init__(self, ip_address, dw=8):
|
||||
self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw))
|
||||
self.source = source = stream.Endpoint(eth_udp_user_description(dw))
|
||||
|
||||
# # #
|
||||
|
||||
self.submodules.depacketizer = depacketizer = LiteEthUDPDepacketizer()
|
||||
self.submodules.depacketizer = depacketizer = LiteEthUDPDepacketizer(dw)
|
||||
self.comb += sink.connect(depacketizer.sink)
|
||||
|
||||
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
|
||||
|
|
@ -192,15 +193,15 @@ class LiteEthUDPRX(Module):
|
|||
# udp
|
||||
|
||||
class LiteEthUDP(Module):
|
||||
def __init__(self, ip, ip_address):
|
||||
self.submodules.tx = tx = LiteEthUDPTX(ip_address)
|
||||
self.submodules.rx = rx = LiteEthUDPRX(ip_address)
|
||||
ip_port = ip.crossbar.get_port(udp_protocol)
|
||||
def __init__(self, ip, ip_address, dw=8):
|
||||
self.submodules.tx = tx = LiteEthUDPTX(ip_address, dw)
|
||||
self.submodules.rx = rx = LiteEthUDPRX(ip_address, dw)
|
||||
ip_port = ip.crossbar.get_port(udp_protocol, dw)
|
||||
self.comb += [
|
||||
tx.source.connect(ip_port.sink),
|
||||
ip_port.source.connect(rx.sink)
|
||||
]
|
||||
self.submodules.crossbar = crossbar = LiteEthUDPCrossbar()
|
||||
self.submodules.crossbar = crossbar = LiteEthUDPCrossbar(dw)
|
||||
self.comb += [
|
||||
crossbar.master.source.connect(tx.sink),
|
||||
rx.source.connect(crossbar.master.sink)
|
||||
|
|
|
|||
|
|
@ -9,9 +9,9 @@ from litex.soc.interconnect.packet import Arbiter, Dispatcher
|
|||
|
||||
|
||||
class LiteEthCrossbar(Module):
|
||||
def __init__(self, master_port, dispatch_param):
|
||||
def __init__(self, master_port, dispatch_param, dw=8):
|
||||
self.users = OrderedDict()
|
||||
self.master = master_port(8)
|
||||
self.master = master_port(dw)
|
||||
self.dispatch_param = dispatch_param
|
||||
|
||||
# overload this in derived classes
|
||||
|
|
|
|||
|
|
@ -14,9 +14,9 @@ class LiteEthMAC(Module, AutoCSR):
|
|||
self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_preamble_crc)
|
||||
self.csrs = []
|
||||
if interface == "crossbar":
|
||||
self.submodules.crossbar = LiteEthMACCrossbar()
|
||||
self.submodules.packetizer = LiteEthMACPacketizer()
|
||||
self.submodules.depacketizer = LiteEthMACDepacketizer()
|
||||
self.submodules.crossbar = LiteEthMACCrossbar(dw)
|
||||
self.submodules.packetizer = LiteEthMACPacketizer(dw)
|
||||
self.submodules.depacketizer = LiteEthMACDepacketizer(dw)
|
||||
self.comb += [
|
||||
self.crossbar.master.source.connect(self.packetizer.sink),
|
||||
self.packetizer.source.connect(self.core.sink),
|
||||
|
|
|
|||
|
|
@ -8,18 +8,18 @@ from litex.soc.interconnect.packet import Depacketizer, Packetizer
|
|||
|
||||
|
||||
class LiteEthMACDepacketizer(Depacketizer):
|
||||
def __init__(self):
|
||||
def __init__(self, dw):
|
||||
Depacketizer.__init__(self,
|
||||
eth_phy_description(8),
|
||||
eth_mac_description(8),
|
||||
eth_phy_description(dw),
|
||||
eth_mac_description(dw),
|
||||
mac_header)
|
||||
|
||||
|
||||
class LiteEthMACPacketizer(Packetizer):
|
||||
def __init__(self):
|
||||
def __init__(self, dw):
|
||||
Packetizer.__init__(self,
|
||||
eth_mac_description(8),
|
||||
eth_phy_description(8),
|
||||
eth_mac_description(dw),
|
||||
eth_phy_description(dw),
|
||||
mac_header)
|
||||
|
||||
|
||||
|
|
@ -41,11 +41,11 @@ class LiteEthMACUserPort(LiteEthMACSlavePort):
|
|||
|
||||
|
||||
class LiteEthMACCrossbar(LiteEthCrossbar):
|
||||
def __init__(self):
|
||||
LiteEthCrossbar.__init__(self, LiteEthMACMasterPort, "ethernet_type")
|
||||
def __init__(self, dw=8):
|
||||
LiteEthCrossbar.__init__(self, LiteEthMACMasterPort, "ethernet_type", dw)
|
||||
|
||||
def get_port(self, ethernet_type):
|
||||
port = LiteEthMACUserPort(8)
|
||||
def get_port(self, ethernet_type, dw=8):
|
||||
port = LiteEthMACUserPort(dw)
|
||||
if ethernet_type in self.users.keys():
|
||||
raise ValueError("Ethernet type {0:#x} already assigned".format(ethernet_type))
|
||||
self.users[ethernet_type] = port
|
||||
|
|
|
|||
Loading…
Reference in a new issue