phy/s7rgmii: cleanup
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@ -43,7 +43,7 @@ class LiteEthPHYRGMIITX(Module):
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class LiteEthPHYRGMIIRX(Module):
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class LiteEthPHYRGMIIRX(Module):
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def __init__(self, pads, rx_delay=2.0e-9):
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def __init__(self, pads, rx_delay=2e-9):
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self.source = source = stream.Endpoint(eth_phy_description(8))
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self.source = source = stream.Endpoint(eth_phy_description(8))
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# # #
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# # #
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@ -117,10 +117,8 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
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]
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]
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# TX
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# TX
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tx_phase = 125e6*tx_delay*360
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tx_phase = 125e6*tx_delay*360
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assert tx_phase < 360
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assert tx_phase < 360
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print(tx_phase)
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pll_locked = Signal()
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pll_locked = Signal()
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pll_fb = Signal()
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pll_fb = Signal()
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