Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

gen: Add clock constraints 

Otherwise the generated verilog is missing necessary "keep" attributes

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2021-09-24 12:19:10 +10:00
parent f2032a4227
commit 63ff6f47e7
1 changed files with 11 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
liteeth/gen.py
View File

@ -207,6 +207,17 @@ class PHYCore(SoCMini):
self.submodules.ethphy = ethphy self.submodules.ethphy = ethphy
self.add_csr("ethphy") self.add_csr("ethphy")
# Generate timing constraints to ensure the "keep" attribute is properly set
# on the various clocks. This also adds the constraints to the generated xdc
# that can then be "imported" in the project using the core.
eth_rx_clk = getattr(ethphy, "crg", ethphy).cd_eth_rx.clk
eth_tx_clk = getattr(ethphy, "crg", ethphy).cd_eth_tx.clk
from liteeth.phy.model import LiteEthPHYModel
if not isinstance(ethphy, LiteEthPHYModel):
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
# MAC Core ----------------------------------------------------------------------------------------- # MAC Core -----------------------------------------------------------------------------------------
class MACCore(PHYCore): class MACCore(PHYCore):