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liteeth/phy: Fix 2500basex linerate.

This commit is contained in:
Florent Kermarrec 2024-01-23 15:44:33 +01:00
parent 4527e8137e
commit 664a633d29
3 changed files with 9 additions and 9 deletions
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10
liteeth/phy/a7_1000basex.py
View File

@ -203,8 +203,8 @@ class A7_1000BASEX(LiteXModule):
# CDR Attributes
p_RXCDR_CFG = {
1.25e9 : 0x0001107FE086021101010,
2.5e9 : 0x0000107FE206001041010,
1.25e9 : 0x0001107FE086021101010,
3.125e9 : 0x0000107FE206001041010,
}[self.linerate],
p_RXCDR_FR_RESET_ON_EIDLE = 0b0,
p_RXCDR_HOLD_DURING_EIDLE = 0b0,
@ -323,10 +323,10 @@ class A7_1000BASEX(LiteXModule):
p_SATA_PLL_CFG = "VCO_3000MHZ",
# RX Fabric Clock Output Control Attributes
p_RXOUT_DIV = {1.25e9 : 4, 2.5e9 : 2}[self.linerate],
p_RXOUT_DIV = {1.25e9 : 4, 3.125e9 : 2}[self.linerate],
# TX Fabric Clock Output Control Attributes
p_TXOUT_DIV = {1.25e9 : 4, 2.5e9 : 2}[self.linerate],
p_TXOUT_DIV = {1.25e9 : 4, 3.125e9 : 2}[self.linerate],
# RX Phase Interpolator Attributes
p_RXPI_CFG0 = 0b000,
@ -785,6 +785,6 @@ class A7_1000BASEX(LiteXModule):
# A7_2500BASEX PHY ---------------------------------------------------------------------------------
class A7_2500BASEX(A7_1000BASEX):
linerate = 2.5e9
linerate = 3.125e9
rx_clk_freq = 312.5e6
tx_clk_freq = 312.5e6

2
liteeth/phy/k7_1000basex.py
View File

@ -802,6 +802,6 @@ class K7_1000BASEX(LiteXModule):
# K7_2500BASEX PHY ---------------------------------------------------------------------------------
class K7_2500BASEX(K7_1000BASEX):
linerate = 2.5e9
linerate = 3.125e9
rx_clk_freq = 312.5e6
tx_clk_freq = 312.5e6

6
liteeth/phy/ku_1000basex.py
View File

@ -291,7 +291,7 @@ class KU_1000BASEX(LiteXModule):
p_RXOOB_CFG = 0b000000110,
p_RXOOB_CLK_CFG = "PMA",
p_RXOSCALRESET_TIME = 0b00011,
p_RXOUT_DIV = {1.25e9 : 4, 2.5e9 : 2}[self.linerate],
p_RXOUT_DIV = {1.25e9 : 4, 3.125e9 : 2}[self.linerate],
p_RXPCSRESET_TIME = 0b00011,
p_RXPHBEACON_CFG = 0b0000000000000000,
p_RXPHDLY_CFG = 0b0010000000100000,
@ -396,7 +396,7 @@ class KU_1000BASEX(LiteXModule):
p_TXFIFO_ADDR_CFG = "LOW",
p_TXGBOX_FIFO_INIT_RD_ADDR = 4,
p_TXGEARBOX_EN = "FALSE",
p_TXOUT_DIV = {1.25e9 : 4, 2.5e9 : 2}[self.linerate],
p_TXOUT_DIV = {1.25e9 : 4, 3.125e9 : 2}[self.linerate],
p_TXPCSRESET_TIME = 0b00011,
p_TXPHDLY_CFG0 = 0b0010000000100000,
p_TXPHDLY_CFG1 = 0b0000000001110101,
@ -860,6 +860,6 @@ class KU_1000BASEX(LiteXModule):
# KU_2500BASEX PHY ---------------------------------------------------------------------------------
class KU_2500BASEX(KU_1000BASEX):
linerate = 2.5e9
linerate = 3.125e9
rx_clk_freq = 312.5e6
tx_clk_freq = 312.5e6