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liteeth
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minimal core reorganization

This commit is contained in:
Victor Suarez Rovere 2022-11-01 11:09:32 -03:00
parent 5f14bd4a7f
commit 68326dafd0
1 changed files with 2 additions and 2 deletions
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4
liteeth/gen.py
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@ -235,6 +235,8 @@ class MACCore(PHYCore):
# Parameters -------------------------------------------------------------------------------
nrxslots = core_config.get("nrxslots", 2)
ntxslots = core_config.get("ntxslots", 2)
eth_bus_standard = core_config["core"]
assert eth_bus_standard in ["wishbone", "axi-lite"]
# PHY --------------------------------------------------------------------------------------
PHYCore.__init__(self, platform, core_config)
@ -249,8 +251,6 @@ class MACCore(PHYCore):
ntxslots = ntxslots,
full_memory_we = core_config.get("full_memory_we", False))
eth_bus_standard = core_config["core"]
assert eth_bus_standard in ["wishbone", "axi-lite"]
if eth_bus_standard == "wishbone":
# Wishbone Interface -----------------------------------------------------------------------
wb_bus = wishbone.Interface()