mac/core: Split TX/RX parts and cleanup to improve readability/maintenance.
This commit is contained in:
Florent Kermarrec
parent
7ed1c61237
commit
6901d418b3
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@ -22,16 +22,17 @@ class LiteEthMACCore(Module, AutoCSR):
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with_sys_datapath = False,
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with_preamble_crc = True,
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with_padding = True):
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core_dw = dw
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# Endpoints.
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self.sink = stream.Endpoint(eth_phy_description(dw))
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self.source = stream.Endpoint(eth_phy_description(dw))
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# Parameters.
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core_dw = dw
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if core_dw < phy.dw:
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raise ValueError("Core data width({}) must be larger than PHY data width({})".format(core_dw, phy.dw))
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rx_pipeline = [phy]
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tx_pipeline = [phy]
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if with_sys_datapath:
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self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw)
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cd_tx = "sys"
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cd_rx = "sys"
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dw = core_dw
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@ -40,30 +41,73 @@ class LiteEthMACCore(Module, AutoCSR):
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cd_rx = "eth_rx"
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dw = phy.dw
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# TX Data-Path (Core --> PHY).
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# ------------------------------------------------------------------------------------------
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self.tx_datapath = tx_datapath = [phy]
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# Early sys conversion.
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if with_sys_datapath:
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self.add_tx_converter(core_dw, phy.dw)
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# Interpacket gap
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tx_gap_inserter = gap.LiteEthMACGap(dw)
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self.submodules += ClockDomainsRenamer(cd_tx)(tx_gap_inserter)
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tx_pipeline.append(tx_gap_inserter)
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tx_gap_inserter = ClockDomainsRenamer(cd_tx)(tx_gap_inserter)
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self.submodules += tx_gap_inserter
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tx_datapath.append(tx_gap_inserter)
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# Preamble / CRC
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if isinstance(phy, LiteEthPHYModel):
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# In simulation, avoid CRC/Preamble to enable direct connection
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# to the Ethernet tap.
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# In simulation, avoid CRC/Preamble to enable direct connection to the Ethernet tap.
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self._preamble_crc = CSRStatus(reset=1)
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elif with_preamble_crc:
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self._preamble_crc = CSRStatus(reset=1)
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# Preamble insert/check
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# Preamble insert.
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preamble_inserter = preamble.LiteEthMACPreambleInserter(dw)
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preamble_checker = preamble.LiteEthMACPreambleChecker(dw)
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self.submodules += ClockDomainsRenamer(cd_tx)(preamble_inserter)
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self.submodules += ClockDomainsRenamer(cd_rx)(preamble_checker)
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tx_pipeline.append(preamble_inserter)
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rx_pipeline.append(preamble_checker)
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preamble_inserter = ClockDomainsRenamer(cd_tx)(preamble_inserter)
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self.submodules += preamble_inserter
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tx_datapath.append(preamble_inserter)
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# CRC insert.
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crc32_inserter = crc.LiteEthMACCRC32Inserter(eth_phy_description(dw))
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crc32_inserter = BufferizeEndpoints({"sink": DIR_SINK})(crc32_inserter)
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crc32_inserter = ClockDomainsRenamer(cd_tx)(crc32_inserter)
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self.submodules += crc32_inserter
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tx_datapath.append(crc32_inserter)
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# Padding
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if with_padding:
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padding_inserter = padding.LiteEthMACPaddingInserter(dw, 60)
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padding_inserter = ClockDomainsRenamer(cd_tx)(padding_inserter)
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self.submodules += padding_inserter
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tx_datapath.append(padding_inserter)
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# Late sys conversion.
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if not with_sys_datapath:
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self.add_tx_converter(core_dw, phy.dw)
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# Data-Path.
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self.submodules.tx_pipeline = stream.Pipeline(*reversed(tx_datapath))
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self.comb += self.sink.connect(self.tx_pipeline.sink)
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# RX Data-Path (PHY --> Core).
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# ------------------------------------------------------------------------------------------
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self.rx_datapath = rx_datapath = [phy]
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# Early sys conversion.
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if with_sys_datapath:
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self.add_rx_converter(core_dw, phy.dw)
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# Preamble / CRC
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if with_preamble_crc:
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# Preamble check.
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preamble_checker = preamble.LiteEthMACPreambleChecker(dw)
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preamble_checker = ClockDomainsRenamer(cd_rx)(preamble_checker)
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self.submodules += preamble_checker
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rx_datapath.append(preamble_checker)
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# Preamble error counter.
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self.submodules.ps_preamble_error = PulseSynchronizer(cd_rx, "sys")
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# Preamble error counter
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self.preamble_errors = CSRStatus(32)
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self.comb += self.ps_preamble_error.i.eq(preamble_checker.error)
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self.sync += [
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@ -71,16 +115,14 @@ class LiteEthMACCore(Module, AutoCSR):
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self.preamble_errors.status.eq(self.preamble_errors.status + 1))
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]
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# CRC insert/check
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crc32_inserter = BufferizeEndpoints({"sink": DIR_SINK})(crc.LiteEthMACCRC32Inserter(eth_phy_description(dw)))
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crc32_checker = BufferizeEndpoints({"sink": DIR_SINK})(crc.LiteEthMACCRC32Checker(eth_phy_description(dw)))
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self.submodules += ClockDomainsRenamer(cd_tx)(crc32_inserter)
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self.submodules += ClockDomainsRenamer(cd_rx)(crc32_checker)
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# CRC check.
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crc32_checker = crc.LiteEthMACCRC32Checker(eth_phy_description(dw))
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crc32_checker = BufferizeEndpoints({"sink": DIR_SINK})(crc32_checker)
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crc32_checker = ClockDomainsRenamer(cd_rx)(crc32_checker)
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self.submodules += crc32_checker
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rx_datapath.append(crc32_checker)
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tx_pipeline.append(crc32_inserter)
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rx_pipeline.append(crc32_checker)
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# CRC error counter
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# CRC error counter.
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self.crc_errors = CSRStatus(32)
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self.submodules.ps_crc_error = PulseSynchronizer(cd_rx, "sys")
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self.comb += self.ps_crc_error.i.eq(crc32_checker.error),
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@ -90,50 +132,67 @@ class LiteEthMACCore(Module, AutoCSR):
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)
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]
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# Padding
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# Padding.
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if with_padding:
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padding_inserter = padding.LiteEthMACPaddingInserter(dw, 60)
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padding_checker = padding.LiteEthMACPaddingChecker(dw, 60)
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self.submodules += ClockDomainsRenamer(cd_tx)(padding_inserter)
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self.submodules += ClockDomainsRenamer(cd_rx)(padding_checker)
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tx_pipeline.append(padding_inserter)
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rx_pipeline.append(padding_checker)
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padding_checker = padding.LiteEthMACPaddingChecker(dw, 60)
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padding_checker = ClockDomainsRenamer(cd_rx)(padding_checker)
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self.submodules += padding_checker
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rx_datapath.append(padding_checker)
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# Late sys conversion.
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if not with_sys_datapath:
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self.data_path_converter(tx_pipeline, rx_pipeline, core_dw, phy.dw)
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self.add_rx_converter(core_dw, phy.dw)
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# Graph
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self.submodules.tx_pipeline = stream.Pipeline(*reversed(tx_pipeline))
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self.submodules.rx_pipeline = stream.Pipeline(*rx_pipeline)
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# Data-Path.
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self.submodules.rx_pipeline = stream.Pipeline(*rx_datapath)
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self.comb += self.rx_pipeline.source.connect(self.source)
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self.sink, self.source = self.tx_pipeline.sink, self.rx_pipeline.source
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def data_path_converter(self, tx_pipeline, rx_pipeline, dw, phy_dw):
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# Delimiters
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def add_tx_converter(self, dw, phy_dw):
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# Delimiters.
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if dw != 8:
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tx_last_be = last_be.LiteEthMACTXLastBE(phy_dw)
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rx_last_be = last_be.LiteEthMACRXLastBE(phy_dw)
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self.submodules += ClockDomainsRenamer("eth_tx")(tx_last_be)
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self.submodules += ClockDomainsRenamer("eth_rx")(rx_last_be)
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tx_pipeline.append(tx_last_be)
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rx_pipeline.append(rx_last_be)
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tx_last_be = ClockDomainsRenamer("eth_tx")(tx_last_be)
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self.submodules += tx_last_be
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self.tx_datapath.append(tx_last_be)
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# Converters
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# Converters.
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if dw != phy_dw:
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tx_converter = stream.StrideConverter(
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description_from = eth_phy_description(dw),
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description_to = eth_phy_description(phy_dw))
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tx_converter = ClockDomainsRenamer("eth_tx")(tx_converter)
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self.submodules += tx_converter
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self.tx_datapath.append(tx_converter)
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# Cross Domain Crossing.
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tx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw),
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cd_from = "sys",
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cd_to = "eth_tx",
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depth = 32)
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self.submodules += tx_cdc
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self.tx_datapath.append(tx_cdc)
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def add_rx_converter(self, dw, phy_dw):
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# Delimiters.
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if dw != 8:
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rx_last_be = last_be.LiteEthMACRXLastBE(phy_dw)
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rx_last_be = ClockDomainsRenamer("eth_rx")(rx_last_be)
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self.submodules += rx_last_be
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self.rx_datapath.append(rx_last_be)
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# Converters.
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if dw != phy_dw:
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rx_converter = stream.StrideConverter(
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description_from = eth_phy_description(phy_dw),
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description_to = eth_phy_description(dw))
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self.submodules += ClockDomainsRenamer("eth_tx")(tx_converter)
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self.submodules += ClockDomainsRenamer("eth_rx")(rx_converter)
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tx_pipeline.append(tx_converter)
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rx_pipeline.append(rx_converter)
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rx_converter = ClockDomainsRenamer("eth_rx")(rx_converter)
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self.submodules += rx_converter
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self.rx_datapath.append(rx_converter)
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# Cross Domain Crossing
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tx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw), cd_from="sys", cd_to="eth_tx", depth=32)
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rx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw), cd_from="eth_rx", cd_to="sys", depth=32)
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self.submodules += tx_cdc, rx_cdc
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tx_pipeline.append(tx_cdc)
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rx_pipeline.append(rx_cdc)
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rx_cdc = stream.ClockDomainCrossing(eth_phy_description(dw),
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cd_from = "eth_rx",
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cd_to = "sys",
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depth = 32)
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self.submodules += rx_cdc
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self.rx_datapath.append(rx_cdc)
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