Update gen.py to work with latest LiteX in wishbone mode

Previously, it would fail with:

$ liteeth/gen.py examples/wishbone_mii.yml
[snip]
Traceback (most recent call last):
  File "liteeth/gen.py", line 346, in <module>
    main()
  File "liteeth/gen.py", line 331, in main
    soc = MACCore(platform, core_config)
  File "liteeth/gen.py", line 244, in __init__
    self.add_wb_master(bridge.wishbone)
  File "[...]/litex/soc/integration/soc_core.py", line 202, in add_wb_master
    self.bus.add_master(master=wbm)
  File "[...]/litex/soc/integration/soc.py", line 347, in add_master
    master = self.add_adapter(name, master, "m2s")
  File "[...]/litex/soc/integration/soc.py", line 316, in add_adapter
    bridge_cls = {
KeyError: (<class 'migen.genlib.record.Record'>, <class 'litex.soc.interconnect.wishbone.Interface'>)

liteeth/gen.py

@@ -234,14 +234,9 @@ class MACCore(PHYCore):
         self.add_csr("ethmac")
 
         # Wishbone Interface -----------------------------------------------------------------------
-        class _WishboneBridge(Module):
-            def __init__(self, interface):
-                self.wishbone = interface
-                self.wishbone.data_width = 32
-
-        bridge = _WishboneBridge(self.platform.request("wishbone"))
-        self.submodules += bridge
-        self.add_wb_master(bridge.wishbone)
+        wb_bus = wishbone.Interface()
+        self.add_wb_master(wb_bus)
+        self.comb += wb_bus.connect_to_pads(self.platform.request("wishbone"), mode="slave")
 
         # Interrupt Interface ----------------------------------------------------------------------
         self.comb += self.platform.request("interrupt").eq(self.ethmac.ev.irq)