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https://github.com/enjoy-digital/liteeth.git
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mac/core: Insert gap in phy tx cd
Otherwise if the sys cd is a bit too fast, the gap generated might get eliminated by the cdc buffer
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parent
8ba5cf06a6
commit
6b81121824
1 changed files with 4 additions and 3 deletions
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@ -95,8 +95,8 @@ class LiteEthMACCore(Module, AutoCSR):
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self.pipeline.append(tx_preamble)
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def add_gap(self):
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tx_gap = gap.LiteEthMACGap(datapath_dw)
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tx_gap = ClockDomainsRenamer(cd_tx)(tx_gap)
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tx_gap = gap.LiteEthMACGap(phy_dw)
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tx_gap = ClockDomainsRenamer("eth_tx")(tx_gap)
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self.submodules += tx_gap
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self.pipeline.append(tx_gap)
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@ -117,7 +117,6 @@ class LiteEthMACCore(Module, AutoCSR):
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if with_preamble_crc:
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tx_datapath.add_crc()
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tx_datapath.add_preamble()
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tx_datapath.add_gap()
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if with_sys_datapath:
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# CHECKME: Verify converter/cdc order for the different cases.
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tx_datapath.add_cdc()
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@ -125,6 +124,8 @@ class LiteEthMACCore(Module, AutoCSR):
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tx_datapath.add_converter()
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if core_dw != 8:
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tx_datapath.add_last_be()
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# Gap insertion has to occurr in phy tx domain to ensure gap is correctly maintained
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tx_datapath.add_gap()
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tx_datapath.pipeline.append(phy)
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self.submodules.tx_datapath = tx_datapath
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