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liteeth
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make phy/usrgmii.py Ultrascale+ compatible

This commit is contained in:
Vamsi Vytla 2023-05-17 14:56:20 -07:00
parent d607d9f34b
commit 7040b19937
1 changed files with 5 additions and 3 deletions
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8
liteeth/phy/usrgmii.py
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@ -52,7 +52,7 @@ class LiteEthPHYRGMIITX(Module):
class LiteEthPHYRGMIIRX(Module): class LiteEthPHYRGMIIRX(Module):
def __init__(self, pads, rx_delay=2e-9): def __init__(self, pads, rx_delay=2e-9, usp=False):
self.source = source = stream.Endpoint(eth_phy_description(8)) self.source = source = stream.Endpoint(eth_phy_description(8))
# # # # # #
@ -77,6 +77,7 @@ class LiteEthPHYRGMIIRX(Module):
p_REFCLK_FREQUENCY = 300.0, p_REFCLK_FREQUENCY = 300.0,
p_DELAY_FORMAT = "TIME", p_DELAY_FORMAT = "TIME",
p_UPDATE_MODE = "ASYNC", p_UPDATE_MODE = "ASYNC",
p_SIM_DEVICE = "ULTRASCALE_PLUS" if usp else "ULTRASCALE",
i_CASC_IN = 0, i_CASC_IN = 0,
i_CASC_RETURN = 0, i_CASC_RETURN = 0,
i_CE = 0, i_CE = 0,
@ -115,6 +116,7 @@ class LiteEthPHYRGMIIRX(Module):
p_REFCLK_FREQUENCY = 300.0, p_REFCLK_FREQUENCY = 300.0,
p_UPDATE_MODE = "ASYNC", p_UPDATE_MODE = "ASYNC",
p_DELAY_FORMAT = "TIME", p_DELAY_FORMAT = "TIME",
p_SIM_DEVICE = "ULTRASCALE_PLUS" if usp else "ULTRASCALE",
i_CASC_IN = 0, i_CASC_IN = 0,
i_CASC_RETURN = 0, i_CASC_RETURN = 0,
i_CE = 0, i_CE = 0,
@ -217,10 +219,10 @@ class LiteEthPHYRGMII(Module, AutoCSR):
dw = 8 dw = 8
tx_clk_freq = 125e6 tx_clk_freq = 125e6
rx_clk_freq = 125e6 rx_clk_freq = 125e6
def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9, usp=False):
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay, usp))
self.sink, self.source = self.tx.sink, self.rx.source self.sink, self.source = self.tx.sink, self.rx.source
if hasattr(pads, "mdc"): if hasattr(pads, "mdc"):