mac/sram: cosmetic changes
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# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2015-2018 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2015-2018 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2017 whitequark <whitequark@whitequark.org>
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# This file is Copyright (c) 2017 whitequark <whitequark@whitequark.org>
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# License: BSD
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# License: BSD
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@ -9,6 +9,8 @@ from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.csr_eventmanager import *
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from litex.soc.interconnect.csr_eventmanager import *
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# LiteEthMACSRAMWriter -----------------------------------------------------------------------------
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class LiteEthMACSRAMWriter(Module, AutoCSR):
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class LiteEthMACSRAMWriter(Module, AutoCSR):
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def __init__(self, dw, depth, nslots=2, endianness="big"):
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def __init__(self, dw, depth, nslots=2, endianness="big"):
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self.sink = sink = stream.Endpoint(eth_phy_description(dw))
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self.sink = sink = stream.Endpoint(eth_phy_description(dw))
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@ -28,10 +30,10 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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# # #
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# # #
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# packet dropped if no slot available
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# Packet dropped if no slot available
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sink.ready.reset = 1
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sink.ready.reset = 1
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# length computation
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# Length computation
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inc = Signal(3)
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inc = Signal(3)
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if endianness == "big":
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if endianness == "big":
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self.comb += Case(sink.last_be, {
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self.comb += Case(sink.last_be, {
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@ -58,18 +60,18 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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counter.eq(counter + inc)
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counter.eq(counter + inc)
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)
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)
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# slot computation
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# Slot computation
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slot = Signal(slotbits)
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slot = Signal(slotbits)
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slot_ce = Signal()
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slot_ce = Signal()
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self.sync += If(slot_ce, slot.eq(slot + 1))
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self.sync += If(slot_ce, slot.eq(slot + 1))
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ongoing = Signal()
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ongoing = Signal()
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# status fifo
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# Status FIFO
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fifo = stream.SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
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fifo = stream.SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
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self.submodules += fifo
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self.submodules += fifo
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# fsm
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# FSM
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fsm = FSM(reset_state="IDLE")
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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self.submodules += fsm
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@ -128,7 +130,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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self._length.status.eq(fifo.source.length),
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self._length.status.eq(fifo.source.length),
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]
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]
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# memory
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# Memory
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mems = [None]*nslots
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mems = [None]*nslots
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ports = [None]*nslots
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ports = [None]*nslots
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for n in range(nslots):
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for n in range(nslots):
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@ -148,6 +150,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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]
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]
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self.comb += Case(slot, cases)
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self.comb += Case(slot, cases)
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# LiteEthMACSRAMReader -----------------------------------------------------------------------------
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class LiteEthMACSRAMReader(Module, AutoCSR):
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class LiteEthMACSRAMReader(Module, AutoCSR):
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def __init__(self, dw, depth, nslots=2, endianness="big"):
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def __init__(self, dw, depth, nslots=2, endianness="big"):
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@ -169,7 +172,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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# # #
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# # #
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# command fifo
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# Command FIFO
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fifo = stream.SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
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fifo = stream.SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
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self.submodules += fifo
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self.submodules += fifo
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self.comb += [
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self.comb += [
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@ -180,7 +183,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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self._level.status.eq(fifo.level)
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self._level.status.eq(fifo.level)
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]
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]
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# length computation
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# Length computation
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counter = Signal(lengthbits)
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counter = Signal(lengthbits)
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counter_reset = Signal()
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counter_reset = Signal()
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counter_ce = Signal()
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counter_ce = Signal()
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@ -192,7 +195,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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)
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)
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# fsm
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# FSM
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last = Signal()
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last = Signal()
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last_d = Signal()
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last_d = Signal()
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@ -245,11 +248,11 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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NextState("IDLE")
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NextState("IDLE")
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)
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)
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# last computation
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# Last computation
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self.comb += last.eq((counter + 4) >= fifo.source.length)
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self.comb += last.eq((counter + 4) >= fifo.source.length)
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self.sync += last_d.eq(last)
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self.sync += last_d.eq(last)
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# memory
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# Memory
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rd_slot = fifo.source.slot
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rd_slot = fifo.source.slot
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mems = [None]*nslots
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mems = [None]*nslots
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