mac/sram: cosmetic changes

liteeth/mac/sram.py

@@ -1,4 +1,4 @@
-# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
 # This file is Copyright (c) 2015-2018 Sebastien Bourdeauducq <sb@m-labs.hk>
 # This file is Copyright (c) 2017 whitequark <whitequark@whitequark.org>
 # License: BSD
@@ -9,6 +9,8 @@ from litex.soc.interconnect.csr import *
 from litex.soc.interconnect.csr_eventmanager import *
 
 
+# LiteEthMACSRAMWriter -----------------------------------------------------------------------------
+
 class LiteEthMACSRAMWriter(Module, AutoCSR):
     def __init__(self, dw, depth, nslots=2, endianness="big"):
         self.sink      = sink = stream.Endpoint(eth_phy_description(dw))
@@ -28,10 +30,10 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
 
         # # #
 
-        # packet dropped if no slot available
+        # Packet dropped if no slot available
         sink.ready.reset = 1
 
-        # length computation
+        # Length computation
         inc = Signal(3)
         if endianness == "big":
             self.comb += Case(sink.last_be, {
@@ -58,18 +60,18 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
                 counter.eq(counter + inc)
             )
 
-        # slot computation
+        # Slot computation
         slot    = Signal(slotbits)
         slot_ce = Signal()
         self.sync += If(slot_ce, slot.eq(slot + 1))
 
         ongoing = Signal()
 
-        # status fifo
+        # Status FIFO
         fifo = stream.SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
         self.submodules += fifo
 
-        # fsm
+        # FSM
         fsm = FSM(reset_state="IDLE")
         self.submodules += fsm
 
@@ -128,7 +130,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
             self._length.status.eq(fifo.source.length),
         ]
 
-        # memory
+        # Memory
         mems  = [None]*nslots
         ports = [None]*nslots
         for n in range(nslots):
@@ -148,6 +150,7 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
             ]
         self.comb += Case(slot, cases)
 
+# LiteEthMACSRAMReader -----------------------------------------------------------------------------
 
 class LiteEthMACSRAMReader(Module, AutoCSR):
     def __init__(self, dw, depth, nslots=2, endianness="big"):
@@ -169,7 +172,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
 
         # # #
 
-        # command fifo
+        # Command FIFO
         fifo = stream.SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
         self.submodules += fifo
         self.comb += [
@@ -180,7 +183,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
             self._level.status.eq(fifo.level)
         ]
 
-        # length computation
+        # Length computation
         counter       = Signal(lengthbits)
         counter_reset = Signal()
         counter_ce    = Signal()
@@ -192,7 +195,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
             )
 
 
-        # fsm
+        # FSM
         last  = Signal()
         last_d = Signal()
 
@@ -245,11 +248,11 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
             NextState("IDLE")
         )
 
-        # last computation
+        # Last computation
         self.comb += last.eq((counter + 4) >= fifo.source.length)
         self.sync += last_d.eq(last)
 
-        # memory
+        # Memory
         rd_slot = fifo.source.slot
 
         mems  = [None]*nslots