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mac/sram: avoid asynchronous read port on LiteEthMACSRAMReader (fix the resource usage issue identified in #43).

This commit is contained in:
Florent Kermarrec 2020-07-13 11:27:25 +02:00
parent 1d76d02ea6
commit 792013a175
1 changed files with 8 additions and 4 deletions
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10
liteeth/mac/sram.py
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@ -173,6 +173,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
]
# Length computation
read_address = Signal(lengthbits)
counter = Signal(lengthbits)
# FSM
@ -180,6 +181,7 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
fsm.act("IDLE",
NextValue(counter, 0),
If(fifo.source.valid,
read_address.eq(0),
NextState("SEND")
)
)
@ -203,11 +205,13 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
fsm.act("SEND",
source.valid.eq(1),
source.last.eq(counter >= (fifo.source.length - 4)),
read_address.eq(counter),
If(source.ready,
read_address.eq(counter + 4),
NextValue(counter, counter + 4),
If(source.last,
NextState("END")
),
)
)
)
fsm.act("END",
@ -222,13 +226,13 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
ports = [None]*nslots
for n in range(nslots):
mems[n] = Memory(dw, depth)
ports[n] = mems[n].get_port(async_read=True) # FIXME: avoid async_read by latching data.
ports[n] = mems[n].get_port()
self.specials += ports[n]
self.mems = mems
cases = {}
for n, port in enumerate(ports):
self.comb += ports[n].adr.eq(counter[2:])
self.comb += ports[n].adr.eq(read_address[2:])
cases[n] = [source.data.eq(port.dat_r)]
self.comb += Case(rd_slot, cases)