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core/arp/LiteEthARPTX: Move datapath outside of FSM (minor logic optimization).

This commit is contained in:
Florent Kermarrec 2021-07-15 18:21:41 +02:00
parent a12d3991e5
commit 7ba5a59e12
1 changed files with 7 additions and 5 deletions
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12
liteeth/core/arp.py
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@ -60,22 +60,24 @@ class LiteEthARPTX(Module):
packetizer.sink.protosize.eq(4), packetizer.sink.protosize.eq(4),
packetizer.sink.sender_mac.eq(mac_address), packetizer.sink.sender_mac.eq(mac_address),
packetizer.sink.sender_ip.eq(ip_address), packetizer.sink.sender_ip.eq(ip_address),
packetizer.sink.target_ip.eq(sink.ip_address),
If(sink.reply, If(sink.reply,
packetizer.sink.opcode.eq(arp_opcode_reply), packetizer.sink.opcode.eq(arp_opcode_reply),
packetizer.sink.target_mac.eq(sink.mac_address), packetizer.sink.target_mac.eq(sink.mac_address),
packetizer.sink.target_ip.eq(sink.ip_address)
).Elif(sink.request, ).Elif(sink.request,
packetizer.sink.opcode.eq(arp_opcode_request), packetizer.sink.opcode.eq(arp_opcode_request),
packetizer.sink.target_mac.eq(0xffffffffffff), packetizer.sink.target_mac.eq(0xffffffffffff),
packetizer.sink.target_ip.eq(sink.ip_address)
) )
] ]
fsm.act("SEND", self.comb += [
packetizer.sink.valid.eq(1), packetizer.source.connect(source, omit={"valid", "ready"}),
packetizer.source.connect(source),
source.target_mac.eq(packetizer.sink.target_mac), source.target_mac.eq(packetizer.sink.target_mac),
source.sender_mac.eq(mac_address), source.sender_mac.eq(mac_address),
source.ethernet_type.eq(ethernet_type_arp), source.ethernet_type.eq(ethernet_type_arp),
]
fsm.act("SEND",
packetizer.sink.valid.eq(1),
packetizer.source.connect(source, keep={"valid", "ready"}),
If(source.valid & source.ready, If(source.valid & source.ready,
NextValue(counter, counter + 1), NextValue(counter, counter + 1),
If(source.last, If(source.last,