[fix] sending last with the last payload
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9f19e7315c
commit
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@ -162,7 +162,7 @@ class LiteEthPHYETHERNETRX(Module):
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self.comb += noise.eq(edge & (bit_period_cnt == 0))
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self.comb += noise.eq(edge & (bit_period_cnt == 0))
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# Byte logic
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# Byte logic
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bitcnt = Signal(max=8)
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bitcnt = Signal(max=8 + 1)
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rx_inverted = Signal()
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rx_inverted = Signal()
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half_bit = Signal()
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half_bit = Signal()
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data_r = Signal(8)
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data_r = Signal(8)
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@ -172,7 +172,7 @@ class LiteEthPHYETHERNETRX(Module):
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).Else(
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).Else(
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source.data.eq(data_r),
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source.data.eq(data_r),
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),
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),
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source.last_be.eq(1),
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source.last_be.eq(source.last),
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]
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]
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self.submodules.fsm = fsm = FSM("SYNC")
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self.submodules.fsm = fsm = FSM("SYNC")
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@ -184,7 +184,7 @@ class LiteEthPHYETHERNETRX(Module):
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)
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)
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fsm.act("SYNC",
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fsm.act("SYNC",
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NextValue(bitcnt, 0),
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NextValue(bitcnt, 1),
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# Wait for the preamble to sync on byte-boundaries
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# Wait for the preamble to sync on byte-boundaries
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If(edge,
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If(edge,
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NextValue(half_bit, ~half_bit),
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NextValue(half_bit, ~half_bit),
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@ -218,9 +218,9 @@ class LiteEthPHYETHERNETRX(Module):
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NextValue(data_r, Cat(data_r[1:], rx_i)),
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NextValue(data_r, Cat(data_r[1:], rx_i)),
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NextValue(bitcnt, bitcnt + 1),
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NextValue(bitcnt, bitcnt + 1),
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NextValue(half_bit, 1),
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NextValue(half_bit, 1),
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If(bitcnt == 7,
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If(bitcnt == 8,
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source.valid.eq(1),
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source.valid.eq(1),
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NextValue(bitcnt, 0),
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NextValue(bitcnt, 1),
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),
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),
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),
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),
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),
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),
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