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phy/ecp5rgmii: review/simplify inband_status integration.
For now keep it specific to ECP5, we'll integrate this soon on the others PHYs, but some other refactoring/merging is required before.
This commit is contained in:
Florent Kermarrec
parent
55af430640
commit
8afdec936d
2 changed files with 44 additions and 53 deletions
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@ -1,4 +1,5 @@
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# This file is Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Shawn Hoffman <godisgovernment@gmail.com>
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# License: BSD
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# RGMII PHY for ECP5 Lattice FPGA
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@ -10,7 +11,6 @@ from litex.build.io import DDROutput, DDRInput
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from liteeth.common import *
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from liteeth.phy.common import *
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from liteeth.phy.rgmii import *
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class LiteEthPHYRGMIITX(Module):
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@ -57,10 +57,26 @@ class LiteEthPHYRGMIITX(Module):
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self.comb += sink.ready.eq(1)
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class LiteEthPHYRGMIIRX(Module):
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def __init__(self, pads, rx_delay=2e-9):
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class LiteEthPHYRGMIIRX(Module, AutoCSR):
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def __init__(self, pads, rx_delay=2e-9, with_inband_status=True):
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self.source = source = stream.Endpoint(eth_phy_description(8))
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self.status = Record(phy_status_layout)
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if with_inband_status:
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self.inband_status = CSRStatus(fields=[
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CSRField("link_status", size=1, values=[
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("``0b0``", "Link down."),
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("``0b1``", "Link up."),
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]),
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CSRField("clock_speed", size=1, values=[
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("``0b00``", "2.5MHz (10Mbps)."),
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("``0b01``", "25MHz (100MBps)."),
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("``0b10``", "125MHz (1000MBps)."),
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]),
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CSRField("duplex_status", size=1, values=[
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("``0b0``", "Half-duplex."),
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("``0b1``", "Full-duplex."),
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]),
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])
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# # #
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@ -68,13 +84,11 @@ class LiteEthPHYRGMIIRX(Module):
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assert rx_delay_taps < 128
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rx_ctl_delayf = Signal()
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rx_ctl_r = Signal()
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rx_ctl_f = Signal()
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rx_ctl_r_reg = self.status.ctl_r
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rx_ctl_f_reg = self.status.ctl_f
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rx_ctl = Signal(2)
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rx_ctl_reg = Signal(2)
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rx_data_delayf = Signal(4)
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rx_data = Signal(8)
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rx_data_reg = self.status.data
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rx_data_reg = Signal(8)
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self.specials += [
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Instance("DELAYF",
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@ -88,15 +102,11 @@ class LiteEthPHYRGMIIRX(Module):
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DDRInput(
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clk = ClockSignal("eth_rx"),
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i = rx_ctl_delayf,
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o1 = rx_ctl_r,
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o2 = rx_ctl_f
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o1 = rx_ctl[0],
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o2 = rx_ctl[1]
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)
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]
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self.sync += [
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rx_ctl_r_reg.eq(rx_ctl_r),
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rx_ctl_f_reg.eq(rx_ctl_f)
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]
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self.sync += rx_ctl_reg.eq(rx_ctl)
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for i in range(4):
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self.specials += [
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Instance("DELAYF",
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@ -116,17 +126,26 @@ class LiteEthPHYRGMIIRX(Module):
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]
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self.sync += rx_data_reg.eq(rx_data)
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rx_ctl_r_reg_d = Signal()
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self.sync += rx_ctl_r_reg_d.eq(rx_ctl_r_reg)
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rx_ctl_reg_d = Signal(2)
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self.sync += rx_ctl_reg_d.eq(rx_ctl_reg)
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last = Signal()
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self.comb += last.eq(~rx_ctl_r_reg & rx_ctl_r_reg_d)
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self.comb += last.eq(~rx_ctl_reg[0] & rx_ctl_reg_d[0])
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self.sync += [
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source.valid.eq(rx_ctl_r_reg),
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source.valid.eq(rx_ctl_reg[0]),
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source.data.eq(rx_data_reg)
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]
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self.comb += source.last.eq(last)
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if with_inband_status:
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self.sync += [
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If(rx_ctl == 0b00,
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self.inband_status.fields.link_status.eq(rx_data[0]),
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self.inband_status.fields.clock_speed.eq(rx_data[1:3]),
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self.inband_status.fields.duplex_status.eq(rx_data[3]),
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)
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]
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class LiteEthPHYRGMIICRG(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset, tx_delay=2e-9):
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@ -182,15 +201,14 @@ class LiteEthPHYRGMII(Module, AutoCSR):
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dw = 8
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tx_clk_freq = 125e6
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rx_clk_freq = 125e6
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def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9, inband_status=True):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True,
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tx_delay = 2e-9,
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rx_delay = 2e-9,
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with_inband_status = True):
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self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay, with_inband_status))
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self.sink, self.source = self.tx.sink, self.rx.source
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if hasattr(pads, "mdc"):
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self.submodules.mdio = LiteEthPHYMDIO(pads)
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if inband_status:
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self.submodules.status = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIStatus())
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self.comb += self.status.phy.eq(self.rx.status)
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@ -1,27 +0,0 @@
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# This file is Copyright (c) 2020 Shawn Hoffman <godisgovernment@gmail.com>
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# License: BSD
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from liteeth.common import *
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phy_status_layout = [
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("ctl_r", 1),
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("ctl_f", 1),
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("data", 8),
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]
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class LiteEthPHYRGMIIStatus(Module):
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def __init__(self):
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self.phy = phy = Record(phy_status_layout)
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# phy_status signals optionally sent during inter-frame
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self.link_up = Signal()
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self.rxc_speed = Signal(2)
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self.full_duplex = Signal()
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inter_frame = Signal()
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self.comb += inter_frame.eq(~(phy.ctl_r | phy.ctl_f))
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self.sync += If(inter_frame,
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self.link_up.eq(phy.data[0]),
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self.rxc_speed.eq(phy.data[1:3]),
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self.full_duplex.eq(phy.data[3]))
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