frontend/etherbone: Simplify code.
This commit is contained in:
Florent Kermarrec
parent
bee34ee955
commit
8f05e72f99
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@ -39,25 +39,16 @@ class LiteEthEtherbonePacketTX(Module):
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self.submodules.packetizer = packetizer = LiteEthEtherbonePacketPacketizer()
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self.comb += [
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packetizer.sink.valid.eq(sink.valid),
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packetizer.sink.last.eq(sink.last),
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sink.ready.eq(packetizer.sink.ready),
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sink.connect(packetizer.sink, keep={"valid", "last", "ready", "data"}),
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sink.connect(packetizer.sink, keep={"pf", "pr", "nr"}),
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packetizer.sink.version.eq(etherbone_version),
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packetizer.sink.magic.eq(etherbone_magic),
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packetizer.sink.port_size.eq(32//8),
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packetizer.sink.addr_size.eq(32//8),
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packetizer.sink.pf.eq(sink.pf),
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packetizer.sink.pr.eq(sink.pr),
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packetizer.sink.nr.eq(sink.nr),
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packetizer.sink.version.eq(etherbone_version),
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packetizer.sink.data.eq(sink.data)
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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packetizer.source.ready.eq(1),
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If(packetizer.source.valid,
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packetizer.source.ready.eq(0),
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NextState("SEND")
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)
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)
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@ -93,43 +84,26 @@ class LiteEthEtherbonePacketRX(Module):
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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depacketizer.source.ready.eq(1),
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If(depacketizer.source.valid,
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depacketizer.source.ready.eq(0),
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NextState("CHECK")
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)
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)
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valid = Signal(reset_less=True)
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self.sync += valid.eq(
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depacketizer.source.valid &
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(depacketizer.source.magic == etherbone_magic)
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)
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fsm.act("CHECK",
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If(valid,
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NextState("PRESENT")
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).Else(
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NextState("DROP")
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NextState("DROP"),
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If(depacketizer.source.magic == etherbone_magic,
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NextState("RECEIVE")
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)
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)
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)
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self.comb += [
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source.last.eq(depacketizer.source.last),
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source.pf.eq(depacketizer.source.pf),
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source.pr.eq(depacketizer.source.pr),
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source.nr.eq(depacketizer.source.nr),
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source.data.eq(depacketizer.source.data),
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depacketizer.source.connect(source, keep={"last", "pf", "pr", "nr", "data"}),
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source.src_port.eq(sink.src_port),
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source.dst_port.eq(sink.dst_port),
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source.ip_address.eq(sink.ip_address),
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source.length.eq(sink.length - etherbone_packet_header.length)
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]
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fsm.act("PRESENT",
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source.valid.eq(depacketizer.source.valid),
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depacketizer.source.ready.eq(source.ready),
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If(source.valid & source.last & source.ready,
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NextState("IDLE")
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fsm.act("RECEIVE",
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depacketizer.source.connect(source, keep={"valid", "ready"}),
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If(source.valid & source.ready,
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If(source.last,
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NextState("IDLE")
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)
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)
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)
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fsm.act("DROP",
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@ -165,9 +139,7 @@ class LiteEthEtherboneProbe(Module):
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ready.eq(1),
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If(sink.valid,
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sink.ready.eq(0),
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NextState("PROBE_RESPONSE")
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)
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)
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@ -175,8 +147,10 @@ class LiteEthEtherboneProbe(Module):
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sink.connect(source),
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source.pf.eq(0),
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source.pr.eq(1),
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If(source.valid & source.last & source.ready,
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NextState("IDLE")
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If(source.valid & source.ready,
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If(source.last,
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NextState("IDLE")
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)
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)
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)
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@ -290,9 +264,7 @@ class LiteEthEtherboneRecordSender(Module):
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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fifo.source.ready.eq(1),
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If(fifo.source.valid,
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fifo.source.ready.eq(0),
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NextState("SEND_BASE_ADDRESS")
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)
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)
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@ -347,9 +319,7 @@ class LiteEthEtherboneRecord(Module):
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last_ip_address = Signal(32, reset_less=True)
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self.sync += [
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If(sink.valid & sink.ready,
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If(first,
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last_ip_address.eq(sink.ip_address),
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),
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If(first, last_ip_address.eq(sink.ip_address)),
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first.eq(sink.last)
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)
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]
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@ -361,8 +331,8 @@ class LiteEthEtherboneRecord(Module):
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sender.source.connect(packetizer.sink),
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packetizer.source.connect(source),
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source.length.eq(etherbone_record_header.length +
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(sender.source.wcount != 0)*4 + sender.source.wcount*4 +
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(sender.source.rcount != 0)*4 + sender.source.rcount*4),
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(sender.source.wcount != 0)*4 + sender.source.wcount*4 +
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(sender.source.rcount != 0)*4 + sender.source.rcount*4),
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source.ip_address.eq(last_ip_address)
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]
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if endianness is "big":
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@ -417,20 +387,17 @@ class LiteEthEtherboneWishboneMaster(Module):
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)
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)
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self.sync += [
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source.base_addr.eq(sink.base_addr),
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source.addr.eq(sink.addr),
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source.count.eq(sink.count),
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source.be.eq(sink.be),
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sink.connect(source, keep={
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"base_addr",
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"addr",
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"count",
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"be"}),
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source.we.eq(1),
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If(data_update,
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source.data.eq(bus.dat_r)
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)
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If(data_update, source.data.eq(bus.dat_r))
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]
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fsm.act("SEND_DATA",
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source.valid.eq(sink.valid),
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source.last.eq(sink.last),
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sink.connect(source, keep={"valid", "last", "ready"}),
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If(source.valid & source.ready,
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sink.ready.eq(1),
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If(source.last,
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NextState("IDLE")
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).Else(
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