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frontend/etherbone: Simplify code.

This commit is contained in:
Florent Kermarrec 2021-09-22 16:45:37 +02:00
parent bee34ee955
commit 8f05e72f99
1 changed files with 28 additions and 61 deletions
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79
liteeth/frontend/etherbone.py
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@ -39,25 +39,16 @@ class LiteEthEtherbonePacketTX(Module):
self.submodules.packetizer = packetizer = LiteEthEtherbonePacketPacketizer() self.submodules.packetizer = packetizer = LiteEthEtherbonePacketPacketizer()
self.comb += [ self.comb += [
packetizer.sink.valid.eq(sink.valid), sink.connect(packetizer.sink, keep={"valid", "last", "ready", "data"}),
packetizer.sink.last.eq(sink.last), sink.connect(packetizer.sink, keep={"pf", "pr", "nr"}),
sink.ready.eq(packetizer.sink.ready), packetizer.sink.version.eq(etherbone_version),
packetizer.sink.magic.eq(etherbone_magic), packetizer.sink.magic.eq(etherbone_magic),
packetizer.sink.port_size.eq(32//8), packetizer.sink.port_size.eq(32//8),
packetizer.sink.addr_size.eq(32//8), packetizer.sink.addr_size.eq(32//8),
packetizer.sink.pf.eq(sink.pf),
packetizer.sink.pr.eq(sink.pr),
packetizer.sink.nr.eq(sink.nr),
packetizer.sink.version.eq(etherbone_version),
packetizer.sink.data.eq(sink.data)
] ]
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
packetizer.source.ready.eq(1),
If(packetizer.source.valid, If(packetizer.source.valid,
packetizer.source.ready.eq(0),
NextState("SEND") NextState("SEND")
) )
) )
@ -93,45 +84,28 @@ class LiteEthEtherbonePacketRX(Module):
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
depacketizer.source.ready.eq(1),
If(depacketizer.source.valid, If(depacketizer.source.valid,
depacketizer.source.ready.eq(0), NextState("DROP"),
NextState("CHECK") If(depacketizer.source.magic == etherbone_magic,
NextState("RECEIVE")
) )
) )
valid = Signal(reset_less=True)
self.sync += valid.eq(
depacketizer.source.valid &
(depacketizer.source.magic == etherbone_magic)
)
fsm.act("CHECK",
If(valid,
NextState("PRESENT")
).Else(
NextState("DROP")
)
) )
self.comb += [ self.comb += [
source.last.eq(depacketizer.source.last), depacketizer.source.connect(source, keep={"last", "pf", "pr", "nr", "data"}),
source.pf.eq(depacketizer.source.pf),
source.pr.eq(depacketizer.source.pr),
source.nr.eq(depacketizer.source.nr),
source.data.eq(depacketizer.source.data),
source.src_port.eq(sink.src_port), source.src_port.eq(sink.src_port),
source.dst_port.eq(sink.dst_port), source.dst_port.eq(sink.dst_port),
source.ip_address.eq(sink.ip_address), source.ip_address.eq(sink.ip_address),
source.length.eq(sink.length - etherbone_packet_header.length) source.length.eq(sink.length - etherbone_packet_header.length)
] ]
fsm.act("PRESENT", fsm.act("RECEIVE",
source.valid.eq(depacketizer.source.valid), depacketizer.source.connect(source, keep={"valid", "ready"}),
depacketizer.source.ready.eq(source.ready), If(source.valid & source.ready,
If(source.valid & source.last & source.ready, If(source.last,
NextState("IDLE") NextState("IDLE")
) )
) )
)
fsm.act("DROP", fsm.act("DROP",
depacketizer.source.ready.eq(1), depacketizer.source.ready.eq(1),
If(depacketizer.source.valid & If(depacketizer.source.valid &
@ -165,9 +139,7 @@ class LiteEthEtherboneProbe(Module):
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
sink.ready.eq(1),
If(sink.valid, If(sink.valid,
sink.ready.eq(0),
NextState("PROBE_RESPONSE") NextState("PROBE_RESPONSE")
) )
) )
@ -175,10 +147,12 @@ class LiteEthEtherboneProbe(Module):
sink.connect(source), sink.connect(source),
source.pf.eq(0), source.pf.eq(0),
source.pr.eq(1), source.pr.eq(1),
If(source.valid & source.last & source.ready, If(source.valid & source.ready,
If(source.last,
NextState("IDLE") NextState("IDLE")
) )
) )
)
# Etherbone Record --------------------------------------------------------------------------------- # Etherbone Record ---------------------------------------------------------------------------------
@ -290,9 +264,7 @@ class LiteEthEtherboneRecordSender(Module):
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
fifo.source.ready.eq(1),
If(fifo.source.valid, If(fifo.source.valid,
fifo.source.ready.eq(0),
NextState("SEND_BASE_ADDRESS") NextState("SEND_BASE_ADDRESS")
) )
) )
@ -347,9 +319,7 @@ class LiteEthEtherboneRecord(Module):
last_ip_address = Signal(32, reset_less=True) last_ip_address = Signal(32, reset_less=True)
self.sync += [ self.sync += [
If(sink.valid & sink.ready, If(sink.valid & sink.ready,
If(first, If(first, last_ip_address.eq(sink.ip_address)),
last_ip_address.eq(sink.ip_address),
),
first.eq(sink.last) first.eq(sink.last)
) )
] ]
@ -417,20 +387,17 @@ class LiteEthEtherboneWishboneMaster(Module):
) )
) )
self.sync += [ self.sync += [
source.base_addr.eq(sink.base_addr), sink.connect(source, keep={
source.addr.eq(sink.addr), "base_addr",
source.count.eq(sink.count), "addr",
source.be.eq(sink.be), "count",
"be"}),
source.we.eq(1), source.we.eq(1),
If(data_update, If(data_update, source.data.eq(bus.dat_r))
source.data.eq(bus.dat_r)
)
] ]
fsm.act("SEND_DATA", fsm.act("SEND_DATA",
source.valid.eq(sink.valid), sink.connect(source, keep={"valid", "last", "ready"}),
source.last.eq(sink.last),
If(source.valid & source.ready, If(source.valid & source.ready,
sink.ready.eq(1),
If(source.last, If(source.last,
NextState("IDLE") NextState("IDLE")
).Else( ).Else(