phy/a7_gtp: Add separators and remove __all__.

This commit is contained in:
Florent Kermarrec 2024-08-19 09:23:38 +02:00
parent c04ac8f698
commit 964df3ac2f
1 changed files with 5 additions and 2 deletions

View File

@ -11,11 +11,11 @@ from math import ceil
from migen import * from migen import *
from migen.genlib.cdc import MultiReg, PulseSynchronizer from migen.genlib.cdc import MultiReg, PulseSynchronizer
__all__ = ["QPLLSettings", "QPLLChannel", "QPLL", "GTPTxInit", "GTPRxInit"] # QPLL Settings ------------------------------------------------------------------------------------
QPLLSettings = namedtuple("QPLLSettings", "refclksel fbdiv fbdiv_45 refclk_div") QPLLSettings = namedtuple("QPLLSettings", "refclksel fbdiv fbdiv_45 refclk_div")
# QPLL Channel -------------------------------------------------------------------------------------
class QPLLChannel: class QPLLChannel:
def __init__(self, index): def __init__(self, index):
@ -25,6 +25,7 @@ class QPLLChannel:
self.clk = Signal() self.clk = Signal()
self.refclk = Signal() self.refclk = Signal()
# QPLL ---------------------------------------------------------------------------------------------
class QPLL(Module): class QPLL(Module):
def __init__(self, def __init__(self,
@ -67,6 +68,7 @@ class QPLL(Module):
**channel_settings **channel_settings
) )
# GTP Tx Init --------------------------------------------------------------------------------------
class GTPTxInit(Module): class GTPTxInit(Module):
def __init__(self, sys_clk_freq): def __init__(self, sys_clk_freq):
@ -126,6 +128,7 @@ class GTPTxInit(Module):
self.done.eq(1) self.done.eq(1)
) )
# GTP Rx Init --------------------------------------------------------------------------------------
# RX Reset Sequence Requirement for Production Silicon: https://www.xilinx.com/support/answers/53561.html # RX Reset Sequence Requirement for Production Silicon: https://www.xilinx.com/support/answers/53561.html
class GTPRxInit(Module): class GTPRxInit(Module):