liteeth/gen: remove semi-colon (thanks @davidcorrigan714).
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@ -200,7 +200,7 @@ class PHYCore(SoCMini):
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pads = platform.request("rgmii_eth"),
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with_hw_init_reset = False) # FIXME: required since sys_clk = eth_rx_clk.
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else:
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raise ValueError("Unsupported PHY");
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raise ValueError("Unsupported PHY")
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self.submodules.ethphy = ethphy
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self.add_csr("ethphy")
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