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https://github.com/enjoy-digital/liteeth.git
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mac/sram: Cleanup/Simplify LiteEthMACSRAMReader.
- Improve signal names. - Use re on memories to simplify addressing (still need to anticipate read by 1 cycle). Also do minor cleanups to LiteEthMACSRAMWriter.
This commit is contained in:
Florent Kermarrec
parent
89dbf17cb6
commit
a00a200547
1 changed files with 57 additions and 46 deletions
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@ -133,63 +133,74 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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]
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if timestamp is not None:
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# Latch Timestamp on start of packet.
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self.sync += If(sink.length == 0, stat_fifo.sink.timestamp.eq(timestamp))
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self.sync += If(length == 0, stat_fifo.sink.timestamp.eq(timestamp))
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self.comb += self._timestamp.status.eq(stat_fifo.source.timestamp)
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# Memory.
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wr_slot = slot
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wr_addr = length[int(math.log2(dw//8)):]
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wr_data = Signal(len(sink.data))
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# Create a Memory per Slot.
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mems = [None] * nslots
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ports = [None] * nslots
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for n in range(nslots):
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mems[n] = Memory(dw, depth)
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mems[n] = Memory(dw, depth)
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ports[n] = mems[n].get_port(write_capable=True)
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self.specials += ports[n]
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self.mems = mems
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data = reverse_bytes(sink.data) if endianness == "big" else sink.data
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# Endianness Handling.
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self.comb += wr_data.eq({"big": reverse_bytes(sink.data), "little": sink.data}[endianness])
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# Connect Memory ports.
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cases = {}
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for n, port in enumerate(ports):
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cases[n] = [
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ports[n].adr.eq(length[int(math.log2(dw//8)):]),
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ports[n].dat_w.eq(data),
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ports[n].adr.eq(wr_addr),
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ports[n].dat_w.eq(wr_data),
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If(sink.valid & write,
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ports[n].we.eq(0xf)
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ports[n].we.eq(2**len(ports[n].we) - 1)
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)
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]
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self.comb += Case(slot, cases)
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self.comb += Case(wr_slot, cases)
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# MAC SRAM Reader ----------------------------------------------------------------------------------
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class LiteEthMACSRAMReader(Module, AutoCSR):
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def __init__(self, dw, depth, nslots=2, endianness="big", timestamp=None):
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assert dw in [32, 64]
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# Endpoint / Signals.
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self.source = source = stream.Endpoint(eth_phy_description(dw))
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slotbits = max(int(math.log2(nslots)), 1)
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lengthbits = bits_for(depth * dw//8)
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self.lengthbits = lengthbits
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# Parameters Check / Compute.
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assert dw in [32, 64]
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slotbits = max(int(math.log2(nslots)), 1)
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lengthbits = bits_for(depth * dw//8)
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# CSRs.
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self._start = CSR()
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self._ready = CSRStatus()
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self._level = CSRStatus(int(math.log2(nslots)) + 1)
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self._slot = CSRStorage(slotbits, reset_less=True)
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self._length = CSRStorage(lengthbits, reset_less=True)
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# Optional Timestamp of the outgoing packets and expose value to software.
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if timestamp is not None:
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# Timestamp the outgoing packets when a Timestamp source is provided
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# and expose value to a software.
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timestampbits = len(timestamp)
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self._timestamp_slot = CSRStatus(slotbits)
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self._timestamp = CSRStatus(timestampbits)
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# Event Manager.
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self.submodules.ev = EventManager()
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self.ev.done = EventSourcePulse() if timestamp is None else EventSourceLevel()
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self.ev.finalize()
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# # #
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start = Signal()
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read = Signal()
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length = Signal(lengthbits)
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# Command FIFO
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# Command FIFO.
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cmd_fifo = stream.SyncFIFO([("slot", slotbits), ("length", lengthbits)], nslots)
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self.submodules += cmd_fifo
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self.comb += [
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@ -209,20 +220,6 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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self.comb += self._timestamp_slot.status.eq(stat_fifo.source.slot)
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self.comb += self._timestamp.status.eq(stat_fifo.source.timestamp)
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# Length computation
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read_address = Signal(lengthbits)
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counter = Signal(lengthbits)
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# FSM
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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NextValue(counter, 0),
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If(cmd_fifo.source.valid,
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start.eq(1),
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NextState("SEND")
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)
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)
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# Encode Length to last_be.
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length_lsb = cmd_fifo.source.length[0:int(math.log2(dw//8))]
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if dw == 32:
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@ -248,19 +245,28 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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})
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)
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fsm.act("SEND",
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# FSM.
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(cmd_fifo.source.valid,
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read.eq(1),
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NextValue(length, dw//8),
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NextState("READ")
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)
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)
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fsm.act("READ",
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source.valid.eq(1),
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source.last.eq(counter >= (cmd_fifo.source.length - dw//8)),
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read_address.eq(counter),
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source.last.eq(length >= cmd_fifo.source.length),
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If(source.ready,
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read_address.eq(counter + dw//8),
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NextValue(counter, counter + dw//8),
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read.eq(1),
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NextValue(length, length + dw//8),
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If(source.last,
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NextState("END")
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NextState("TERMINATE")
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)
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)
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)
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fsm.act("END",
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fsm.act("TERMINATE",
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NextValue(length, 0),
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self.ev.done.trigger.eq(1),
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cmd_fifo.source.ready.eq(1),
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NextState("IDLE")
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@ -268,32 +274,37 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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if timestamp is not None:
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# Latch Timestamp on start of outgoing packet.
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self.sync += If(start, stat_fifo.sink.timestamp.eq(timestamp))
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self.sync += If(length == 0, stat_fifo.sink.timestamp.eq(timestamp))
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self.comb += stat_fifo.sink.valid.eq(fsm.ongoing("END"))
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self.comb += stat_fifo.sink.slot.eq(cmd_fifo.source.slot)
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# Trigger event when Status FIFO has contents (Override FSM assignment).
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self.comb += self.ev.done.trigger.eq(stat_fifo.source.valid)
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# Memory
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# Memory.
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rd_slot = cmd_fifo.source.slot
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rd_addr = Signal(lengthbits)
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rd_data = Signal(len(source.data))
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# Create a Memory per Slot.
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mems = [None]*nslots
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ports = [None]*nslots
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for n in range(nslots):
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mems[n] = Memory(dw, depth)
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ports[n] = mems[n].get_port()
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ports[n] = mems[n].get_port(has_re=True)
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self.specials += ports[n]
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self.mems = mems
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data = Signal().like(source.data)
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# Connect Memory ports.
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cases = {}
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for n, port in enumerate(ports):
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self.comb += ports[n].adr.eq(read_address[int(math.log2(dw//8)):])
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cases[n] = [data.eq(port.dat_r)]
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self.comb += ports[n].re.eq(read)
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self.comb += ports[n].adr.eq(length[int(math.log2(dw//8)):])
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cases[n] = [rd_data.eq(port.dat_r)]
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self.comb += [
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Case(rd_slot, cases),
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source.data.eq(reverse_bytes(data) if endianness == "big" else data),
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]
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self.comb += Case(rd_slot, cases)
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# Endianness Handling.
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self.comb += source.data.eq({"big" : reverse_bytes(rd_data), "little": rd_data}[endianness])
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# MAC SRAM -----------------------------------------------------------------------------------------
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