change MAC location (next to phy/core/frontend), keep import retro-compatibility

liteeth/core/__init__.py

@@ -1,11 +1,10 @@
 from liteeth.common import *
-from liteeth.core.mac import LiteEthMAC
+from liteeth.mac import LiteEthMAC
 from liteeth.core.arp import LiteEthARP
 from liteeth.core.ip import LiteEthIP
 from liteeth.core.udp import LiteEthUDP
 from liteeth.core.icmp import LiteEthICMP
 
-
 class LiteEthIPCore(Module, AutoCSR):
     def __init__(self, phy, mac_address, ip_address, clk_freq, with_icmp=True):
         self.submodules.mac = LiteEthMAC(phy, 8, interface="crossbar", with_preamble_crc=True)

liteeth/core/mac.py

@@ -0,0 +1 @@
+from liteeth.mac import * # retro-compatibility # FIXME: remove

liteeth/mac/__init__.py

@@ -1,7 +1,7 @@
 from liteeth.common import *
-from liteeth.core.mac.common import *
+from liteeth.mac.common import *
-from liteeth.core.mac.core import LiteEthMACCore
+from liteeth.mac.core import LiteEthMACCore
-from liteeth.core.mac.wishbone import LiteEthMACWishboneInterface
+from liteeth.mac.wishbone import LiteEthMACWishboneInterface
 
 
 class LiteEthMAC(Module, AutoCSR):

liteeth/mac/core.py

@@ -1,5 +1,5 @@
 from liteeth.common import *
-from liteeth.core.mac import gap, preamble, crc, padding, last_be
+from liteeth.mac import gap, preamble, crc, padding, last_be
 from liteeth.phy.model import LiteEthPHYModel
 
 from migen.genlib.cdc import PulseSynchronizer

liteeth/mac/wishbone.py

@@ -1,7 +1,7 @@
 from migen.fhdl.simplify import FullMemoryWE
 
 from liteeth.common import *
-from liteeth.core.mac import sram
+from liteeth.mac import sram
 
 from litex.soc.interconnect import wishbone