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phy/s6rgmii: fix missing last signal
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@ -59,6 +59,8 @@ class LiteEthPHYRGMIIRX(Module):
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rx_ctl_d = Signal()
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self.sync += rx_ctl_d.eq(rx_ctl)
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last = Signal()
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self.comb += last.eq(~rx_ctl & rx_ctl_d)
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self.sync += [
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source.valid.eq(rx_ctl),
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source.data.eq(rx_data)
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