phy/rmii: Add with_refclk_ddr_ouptut parameter and minor cosmetic cleanups.
Setting with_refclk_ddr_ouptut to False can allow use of RMII PHY on platforms not supporting DDROutput.
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@ -1,7 +1,7 @@
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2015-2023 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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@ -25,16 +25,17 @@ class LiteEthPHYRMIITX(Module):
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# # #
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converter = stream.StrideConverter(converter_description(8),
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converter_description(2))
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self.submodules += converter
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self.submodules.converter = converter = stream.StrideConverter(
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description_from = converter_description(8),
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description_to = converter_description(2),
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)
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self.comb += [
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converter.sink.valid.eq(sink.valid),
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converter.sink.data.eq(sink.data),
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sink.ready.eq(converter.sink.ready),
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converter.source.ready.eq(1)
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]
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pads.tx_en.reset_less = True
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pads.tx_en.reset_less = True
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pads.tx_data.reset_less = True
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self.sync += [
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pads.tx_en.eq(converter.source.valid),
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@ -48,22 +49,24 @@ class LiteEthPHYRMIIRX(Module):
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# # #
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converter = stream.StrideConverter(converter_description(2),
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converter_description(8))
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converter = stream.StrideConverter(
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description_from = converter_description(2),
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description_to = converter_description(8),
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)
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converter = ResetInserter()(converter)
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self.submodules += converter
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self.submodules.converter = converter
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converter_sink_valid = Signal()
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converter_sink_data = Signal(2)
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converter_sink_data = Signal(2)
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self.specials += [
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MultiReg(converter_sink_valid, converter.sink.valid, n=2),
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MultiReg(converter_sink_data, converter.sink.data, n=2)
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MultiReg(converter_sink_data, converter.sink.data, n=2)
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]
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crs_dv = Signal()
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crs_dv = Signal()
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crs_dv_d = Signal()
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rx_data = Signal(2)
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rx_data = Signal(2)
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self.sync += [
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crs_dv.eq(pads.crs_dv),
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crs_dv_d.eq(crs_dv),
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@ -83,7 +86,7 @@ class LiteEthPHYRMIIRX(Module):
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fsm.act("RECEIVE",
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converter_sink_valid.eq(1),
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converter_sink_data.eq(rx_data),
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# end of frame when 2 consecutives 0 on crs_dv
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# End of frame when 2 consecutives 0 on crs_dv.
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If(~(crs_dv | crs_dv_d),
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converter.sink.last.eq(1),
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NextState("IDLE")
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@ -93,7 +96,9 @@ class LiteEthPHYRMIIRX(Module):
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class LiteEthPHYRMIICRG(Module, AutoCSR):
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def __init__(self, clock_pads, pads, refclk_cd, with_hw_init_reset):
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def __init__(self, clock_pads, pads, refclk_cd,
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with_hw_init_reset = True,
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with_refclk_ddr_output = True):
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self._reset = CSRStorage()
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# # #
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@ -114,7 +119,10 @@ class LiteEthPHYRMIICRG(Module, AutoCSR):
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self.comb += self.cd_eth_tx.clk.eq(ClockSignal(refclk_cd))
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# Drive clock_pads if provided.
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if clock_pads is not None:
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self.specials += DDROutput(0, 1, clock_pads.ref_clk, ClockSignal("eth_tx"))
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if with_refclk_ddr_output:
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self.specials += DDROutput(i1=0, i2=1, o=clock_pads.ref_clk, clk=ClockSignal("eth_tx"))
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else:
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self.comb += clock_pads.ref_clk.eq(~ClockSignal("eth_tx")) # CHEKCME: Keep Invert?
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# Reset
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self.reset = reset = Signal()
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@ -135,10 +143,15 @@ class LiteEthPHYRMII(Module, AutoCSR):
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dw = 8
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tx_clk_freq = 50e6
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rx_clk_freq = 50e6
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def __init__(self, clock_pads, pads, refclk_cd="eth", with_hw_init_reset=True):
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self.submodules.crg = LiteEthPHYRMIICRG(clock_pads, pads, refclk_cd, with_hw_init_reset)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRMIIRX(pads))
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def __init__(self, clock_pads, pads, refclk_cd="eth",
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with_hw_init_reset = True,
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with_refclk_ddr_output = True):
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self.submodules.crg = LiteEthPHYRMIICRG(clock_pads, pads, refclk_cd,
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with_hw_init_reset = with_hw_init_reset,
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with_refclk_ddr_output = with_refclk_ddr_output,
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)
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self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads))
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self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRMIIRX(pads))
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self.sink, self.source = self.tx.sink, self.rx.source
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if hasattr(pads, "mdc"):
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