Merge pull request #88 from lschuermann/dev/wtfverilog
{De,P}acketizer: fix source.last assignment between the two FSMs
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enjoy-digital
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commit
b6c5e41097
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@ -43,6 +43,10 @@ class Packetizer(Module):
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if header_words != 1:
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self.sync += If(sr_shift, sr.eq(sr[data_width:]))
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source_last_a = Signal()
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source_last_b = Signal()
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source_last_s = Signal()
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# FSM.
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm_from_idle = Signal()
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@ -52,7 +56,7 @@ class Packetizer(Module):
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If(sink.valid,
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sink.ready.eq(0),
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source.valid.eq(1),
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source.last.eq(0),
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source_last_a.eq(0),
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source.data.eq(self.header[:data_width]),
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If(source.valid & source.ready,
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sr_load.eq(1),
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@ -67,7 +71,7 @@ class Packetizer(Module):
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)
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fsm.act("HEADER-SEND",
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source.valid.eq(1),
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source.last.eq(0),
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source_last_a.eq(0),
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source.data.eq(sr[min(data_width, len(sr)-1):]),
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If(source.valid & source.ready,
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sr_shift.eq(1),
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@ -82,7 +86,7 @@ class Packetizer(Module):
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)
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fsm.act("ALIGNED-DATA-COPY",
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source.valid.eq(sink.valid),
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source.last.eq(sink.last),
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source_last_a.eq(sink.last),
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source.data.eq(sink.data),
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If(source.valid & source.ready,
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sink.ready.eq(1),
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@ -96,7 +100,7 @@ class Packetizer(Module):
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self.sync += If(source.ready, sink_d.eq(sink))
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fsm.act("UNALIGNED-DATA-COPY",
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source.valid.eq(sink.valid | sink_d.last),
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source.last.eq(sink.last | sink_d.last),
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source_last_a.eq(sink.last | sink_d.last),
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If(fsm_from_idle,
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source.data[:max(header_leftover*8, 1)].eq(sr[min(header_offset_multiplier*data_width, len(sr)-1):])
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).Else(
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@ -161,7 +165,8 @@ class Packetizer(Module):
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If(in_data_copy & sink.last & (sink_last_be > new_last_be),
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# Right shift did not wrap around, need to delay the
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# calculated last_be value and last by one cycle.
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source.last.eq(0),
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source_last_b.eq(0),
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source_last_s.eq(1),
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source.last_be.eq(0),
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If(source.ready & source.valid,
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NextValue(delayed_last_be, new_last_be),
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@ -170,7 +175,8 @@ class Packetizer(Module):
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).Elif(in_data_copy,
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# Output the calculated last_be value on the current packet
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# already. For the next sink packet, ignore any last_be
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source.last.eq(sink.last),
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source_last_b.eq(sink.last),
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source_last_s.eq(1),
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source.last_be.eq(new_last_be),
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),
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If(in_data_copy,
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@ -182,7 +188,8 @@ class Packetizer(Module):
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self.last_be_fsm.act("DELAYED",
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# Output the delayed last and last_be signals
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source.last.eq(1),
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source_last_b.eq(1),
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source_last_s.eq(1),
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source.last_be.eq(delayed_last_be),
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sink.ready.eq(0),
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If(source.ready,
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@ -190,6 +197,14 @@ class Packetizer(Module):
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),
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)
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self.comb += [
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If(source_last_s,
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source.last.eq(source_last_b),
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).Else(
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source.last.eq(source_last_a),
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)
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]
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# Error.
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if hasattr(sink, "error") and hasattr(source, "error"):
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self.comb += source.error.eq(sink.error)
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@ -229,6 +244,10 @@ class Depacketizer(Module):
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self.comb += self.header.eq(sr)
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self.comb += header.decode(self.header, source)
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source_last_a = Signal()
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source_last_b = Signal()
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source_last_s = Signal()
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# FSM.
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm_from_idle = Signal()
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@ -258,7 +277,7 @@ class Depacketizer(Module):
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)
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fsm.act("ALIGNED-DATA-COPY",
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source.valid.eq(sink.valid | sink_d.last),
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source.last.eq(sink.last | sink_d.last),
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source_last_a.eq(sink.last | sink_d.last),
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sink.ready.eq(source.ready),
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source.data.eq(sink.data),
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If(source.valid & source.ready,
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@ -272,7 +291,7 @@ class Depacketizer(Module):
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self.sync += If(sink.valid & sink.ready, sink_d.eq(sink))
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fsm.act("UNALIGNED-DATA-COPY",
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source.valid.eq(sink.valid | sink_d.last),
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source.last.eq(sink_d.last),
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source_last_a.eq(sink_d.last),
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sink.ready.eq(source.ready & ~source.last),
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source.data.eq(sink_d.data[header_leftover*8:]),
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source.data[min((bytes_per_clk-header_leftover)*8, data_width-1):].eq(sink.data),
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@ -351,7 +370,8 @@ class Depacketizer(Module):
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If(sink.valid & sink.last & (sink_last_be > new_last_be),
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# last_be did wrap around. Need to delay the calculated
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# last_be value and last by one cycle.
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source.last.eq(0),
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source_last_b.eq(0),
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source_last_s.eq(1),
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source.last_be.eq(0),
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# Normally just wait until a source bus transaction occurred
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# (ready + valid) until the delayed last_be can be
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@ -369,7 +389,8 @@ class Depacketizer(Module):
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),
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).Elif(sink.last,
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# Simply forward the calculated last_be value.
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source.last.eq(1),
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source_last_b.eq(1),
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source_last_s.eq(1),
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source.last_be.eq(new_last_be),
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),
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If(self.fsm.ongoing("ALIGNED-DATA-COPY") \
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@ -382,10 +403,19 @@ class Depacketizer(Module):
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self.last_be_fsm.act("DELAYED",
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# Output the delayed last and last_be signals
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source.last.eq(1),
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source_last_b.eq(1),
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source_last_s.eq(1),
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source.last_be.eq(delayed_last_be),
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sink.ready.eq(0),
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If(source.ready & source.valid,
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NextState("DEFAULT"),
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),
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)
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self.comb += [
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If(source_last_s,
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source.last.eq(source_last_b),
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).Else(
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source.last.eq(source_last_a),
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),
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]
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