global: reset_less optimizations

liteeth/core/arp.py

@@ -30,7 +30,7 @@ class LiteEthARPTX(Module):
 
         self.submodules.packetizer = packetizer = LiteEthARPPacketizer()
 
-        counter = Signal(max=max(arp_header.length, eth_min_len))
+        counter = Signal(max=max(arp_header.length, eth_min_len), reset_less=True)
         counter_reset = Signal()
         counter_ce = Signal()
         self.sync += \
@@ -111,7 +111,7 @@ class LiteEthARPRX(Module):
                 NextState("CHECK")
             )
         )
-        valid = Signal()
+        valid = Signal(reset_less=True)
         self.sync += valid.eq(
             depacketizer.source.valid &
             (depacketizer.source.hwtype == arp_hwtype_ethernet) &
@@ -169,7 +169,7 @@ class LiteEthARPTable(Module):
                 request_pending.eq(1)
             )
 
-        request_ip_address = Signal(32)
+        request_ip_address = Signal(32, reset_less=True)
         request_ip_address_reset = Signal()
         request_ip_address_update = Signal()
         self.sync += \
@@ -197,8 +197,8 @@ class LiteEthARPTable(Module):
         # targeting multiple destinations.
         update = Signal()
         cached_valid = Signal()
-        cached_ip_address = Signal(32)
-        cached_mac_address = Signal(48)
+        cached_ip_address = Signal(32, reset_less=True)
+        cached_mac_address = Signal(48, reset_less=True)
         cached_timer = WaitTimer(clk_freq*10)
         self.submodules += cached_timer
 
@@ -241,7 +241,6 @@ class LiteEthARPTable(Module):
                 )
             )
         self.comb += cached_timer.wait.eq(~update)
-        found = Signal()
         fsm.act("CHECK_TABLE",
             If(cached_valid,
                 If(request_ip_address == cached_ip_address,

liteeth/core/icmp.py

@@ -78,7 +78,7 @@ class LiteEthICMPRX(Module):
                 NextState("CHECK")
             )
         )
-        valid = Signal()
+        valid = Signal(reset_less=True)
         self.sync += valid.eq(
             depacketizer.source.valid &
             (sink.protocol == icmp_protocol)

liteeth/core/ip.py

@@ -48,15 +48,15 @@ class LiteEthIPV4Checksum(Module):
 
         # # #
 
-        s = Signal(17)
-        r = Signal(17)
+        s = Signal(17, reset_less=True)
+        r = Signal(17, reset_less=True)
         n_cycles = 0
         for i in range(ipv4_header.length//2):
             if skip_checksum and (i == ipv4_header.fields["checksum"].byte//2):
                 pass
             else:
-                s_next = Signal(17)
-                r_next = Signal(17)
+                s_next = Signal(17, reset_less=True)
+                r_next = Signal(17, reset_less=True)
                 self.comb += s_next.eq(r + self.header[i*16:(i+1)*16])
                 r_next_eq = r_next.eq(Cat(s_next[:16]+s_next[16], Signal()))
                 if (i%words_per_clock_cycle) != 0:
@@ -120,7 +120,7 @@ class LiteEthIPTX(Module):
             packetizer.sink.checksum.eq(checksum.value)
         ]
 
-        target_mac = Signal(48)
+        target_mac = Signal(48, reset_less=True)
 
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
@@ -205,7 +205,7 @@ class LiteEthIPRX(Module):
                 NextState("CHECK")
             )
         )
-        valid = Signal()
+        valid = Signal(reset_less=True)
         self.sync += valid.eq(
             depacketizer.source.valid &
             (depacketizer.source.target_ip == ip_address) &

liteeth/core/mac/gap.py

@@ -11,7 +11,7 @@ class LiteEthMACGap(Module):
         # # #
 
         gap = math.ceil(eth_interpacket_gap/(dw//8))
-        counter = Signal(max=gap)
+        counter = Signal(max=gap, reset_less=True)
         counter_reset = Signal()
         counter_ce = Signal()
         self.sync += \

liteeth/core/mac/preamble.py

@@ -12,7 +12,7 @@ class LiteEthMACPreambleInserter(Module):
 
         preamble = Signal(64, reset=eth_preamble)
         cnt_max = (64//dw)-1
-        cnt = Signal(max=cnt_max+1)
+        cnt = Signal(max=cnt_max+1, reset_less=True)
         clr_cnt = Signal()
         inc_cnt = Signal()
 
@@ -65,7 +65,7 @@ class LiteEthMACPreambleChecker(Module):
 
         preamble = Signal(64, reset=eth_preamble)
         cnt_max = (64//dw) - 1
-        cnt = Signal(max=cnt_max+1)
+        cnt = Signal(max=cnt_max+1, reset_less=True)
         clr_cnt = Signal()
         inc_cnt = Signal()
 
@@ -76,7 +76,7 @@ class LiteEthMACPreambleChecker(Module):
                 cnt.eq(cnt+1)
             )
 
-        discard = Signal()
+        discard = Signal(reset_less=True)
         clr_discard = Signal()
         set_discard = Signal()
 

liteeth/core/udp.py

@@ -147,7 +147,7 @@ class LiteEthUDPRX(Module):
                 NextState("CHECK")
             )
         )
-        valid = Signal()
+        valid = Signal(reset_less=True)
         self.sync += valid.eq(
             depacketizer.source.valid &
             (sink.protocol == udp_protocol)

liteeth/frontend/etherbone.py

@@ -93,7 +93,7 @@ class LiteEthEtherbonePacketRX(Module):
                 NextState("CHECK")
             )
         )
-        valid = Signal()
+        valid = Signal(reset_less=True)
         self.sync += valid.eq(
             depacketizer.source.valid &
             (depacketizer.source.magic == etherbone_magic)
@@ -205,11 +205,11 @@ class LiteEthEtherboneRecordReceiver(Module):
         self.submodules += fifo
         self.comb += sink.connect(fifo.sink)
 
-        base_addr = Signal(32)
+        base_addr = Signal(32, reset_less=True)
         base_addr_update = Signal()
         self.sync += If(base_addr_update, base_addr.eq(fifo.source.data))
 
-        counter = Signal(max=512)
+        counter = Signal(max=512, reset_less=True)
         counter_reset = Signal()
         counter_ce = Signal()
         self.sync += \
@@ -344,7 +344,7 @@ class LiteEthEtherboneRecord(Module):
 
         # save last ip address
         first = Signal(reset=1)
-        last_ip_address = Signal(32)
+        last_ip_address = Signal(32, reset_less=True)
         self.sync += [
             If(sink.valid & sink.ready,
                 If(first,
@@ -380,7 +380,7 @@ class LiteEthEtherboneWishboneMaster(Module):
 
         # # #
 
-        data = Signal(32)
+        data = Signal(32, reset_less=True)
         data_update = Signal()
         self.sync += If(data_update, data.eq(bus.dat_r))
 

liteeth/phy/gmii.py

@@ -13,7 +13,10 @@ class LiteEthPHYGMIITX(Module):
         # # #
 
         if hasattr(pads, "tx_er"):
+            pads.tx_er.reset_less = True
             self.sync += pads.tx_er.eq(0)
+        pads.tx_en.reset_less = True
+        pads.tx_data.reset_less = True
         self.sync += [
             pads.tx_en.eq(sink.valid),
             pads.tx_data.eq(sink.data),

liteeth/phy/gmii_mii.py

@@ -43,8 +43,12 @@ class LiteEthPHYGMIIMIITX(Module):
             demux.source1.connect(mii_tx.sink),
         ]
 
+
         if hasattr(pads, "tx_er"):
+            pads.tx_er.reset_less = True
             self.comb += pads.tx_er.eq(0)
+        pads.tx_en.reset_less = True
+        pads.tx_data.reset_less = True
         self.sync += [
             If(mode == modes["MII"],
                 pads.tx_en.eq(mii_tx_pads.tx_en),
@@ -63,6 +67,8 @@ class LiteEthPHYGMIIMIIRX(Module):
         # # #
 
         pads_d = Record(rx_pads_layout)
+        pads_d.dv.reset_less = True
+        pads_d.rx_data.reset_less = True
         self.sync += [
             pads_d.dv.eq(pads.dv),
             pads_d.rx_data.eq(pads.rx_data)
@@ -107,7 +113,7 @@ class LiteEthGMIIMIIModeDetection(Module, AutoCSR):
 
         # Generate a tick every 1024 clock cycles (eth_rx clock domain)
         eth_tick = Signal()
-        eth_counter = Signal(10)
+        eth_counter = Signal(10, reset_less=True)
         self.sync.eth_rx += eth_counter.eq(eth_counter + 1)
         self.comb += eth_tick.eq(eth_counter == 0)
 
@@ -121,7 +127,7 @@ class LiteEthGMIIMIIModeDetection(Module, AutoCSR):
         self.submodules += eth_ps
 
         # sys_clk domain counter
-        sys_counter = Signal(24)
+        sys_counter = Signal(24, reset_less=True)
         sys_counter_reset = Signal()
         sys_counter_ce = Signal()
         self.sync += [

liteeth/phy/mii.py

@@ -17,6 +17,7 @@ class LiteEthPHYMIITX(Module):
         # # #
 
         if hasattr(pads, "tx_er"):
+            pads.tx_er.reset_less = True
             self.sync += pads.tx_er.eq(0)
         converter = stream.StrideConverter(converter_description(8),
                                            converter_description(4))
@@ -27,6 +28,8 @@ class LiteEthPHYMIITX(Module):
             sink.ready.eq(converter.sink.ready),
             converter.source.ready.eq(1)
         ]
+        pads.tx_en.reset_less = True
+        pads.tx_data.reset_less = True
         self.sync += [
             pads.tx_en.eq(converter.source.valid),
             pads.tx_data.eq(converter.source.data)

liteeth/phy/rmii.py

@@ -28,6 +28,8 @@ class LiteEthPHYRMIITX(Module):
             sink.ready.eq(converter.sink.ready),
             converter.source.ready.eq(1)
         ]
+        pads.tx_en.reset_less = True
+        pads.tx_data.reset_less = True
         self.sync += [
             pads.tx_en.eq(converter.source.valid),
             pads.tx_data.eq(converter.source.data)