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frontend/stream: Switch FIFOs to buffered.

This commit is contained in:
Florent Kermarrec 2022-02-03 15:58:06 +01:00
parent 35b475727c
commit b903b7257b
1 changed files with 2 additions and 2 deletions
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4
liteeth/frontend/stream.py
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@ -31,7 +31,7 @@ class LiteEthStream2UDPTX(Module):
level = Signal(max=fifo_depth+1) level = Signal(max=fifo_depth+1)
counter = Signal(max=fifo_depth+1) counter = Signal(max=fifo_depth+1)
self.submodules.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth) self.submodules.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth, buffered=True)
self.comb += sink.connect(fifo.sink) self.comb += sink.connect(fifo.sink)
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="IDLE")
@ -87,7 +87,7 @@ class LiteEthUDP2StreamRX(Module):
sink.ready.eq(source.ready | ~valid) sink.ready.eq(source.ready | ~valid)
] ]
else: else:
self.submodules.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth) self.submodules.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth, buffered=True)
self.comb += [ self.comb += [
sink.connect(fifo.sink, keep={"last", "data"}), sink.connect(fifo.sink, keep={"last", "data"}),
fifo.sink.valid.eq(sink.valid & valid), fifo.sink.valid.eq(sink.valid & valid),