frontend/stream: Switch FIFOs to buffered.
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@ -31,7 +31,7 @@ class LiteEthStream2UDPTX(Module):
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level = Signal(max=fifo_depth+1)
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counter = Signal(max=fifo_depth+1)
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self.submodules.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth)
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self.submodules.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth, buffered=True)
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self.comb += sink.connect(fifo.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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@ -87,7 +87,7 @@ class LiteEthUDP2StreamRX(Module):
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sink.ready.eq(source.ready | ~valid)
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]
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else:
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self.submodules.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth)
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self.submodules.fifo = fifo = stream.SyncFIFO([("data", data_width)], fifo_depth, buffered=True)
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self.comb += [
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sink.connect(fifo.sink, keep={"last", "data"}),
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fifo.sink.valid.eq(sink.valid & valid),
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