[enh] added bench
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Charles-Henri Mousset
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#!/usr/bin/env python3
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Charles-Henri Mousset <ch.mousset@gmail.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import digilent_arty
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
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from litex_boards.targets.digilent_arty import _CRG, BaseSoC
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from litex.build.generic_platform import *
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from litex.soc.cores.clock import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from liteeth.phy.mii import LiteEthPHYMII
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from liteeth.phy.ethernet import LiteEthPHYETHERNET
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from litescope import LiteScopeAnalyzer
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# PMOD Raw 10BASET Ethernet ------------------------------------------------------------------------
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#
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# This testbench uses 2 differential pairs of the Arty-A7, and 4 outputs to bias the termination
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# resistors.
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# Two(2) 100 Ohms resistor (termination), four(4) 1kOhms (bias) resistors and four(4) capacitors are
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# required to connect to the Ethernet port.
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# Both the TX and RX pairs are wired identically.
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# Using the 4 IOs as pullup/down are not strictly required (you can bias to GND/3V3 instead), but it
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# makes wiring very convenient using only a piece of proto-PCB and SMD components.
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#
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# Ideally the capacitors should be replaced with suitable transformers, but for short
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# wiring the capacitors usually work well.
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#
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# +───────PMOD Pinout───────+
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# | 7 td_p_pd | td_p 1 |
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# | 8 td_n_pu | td_n 2 |
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# | 9 rd_p_pd | rd_p 3 |
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# | 10 rd_n_pu | rd_n 4 |
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# | 11 GND | GND 5 |
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# | 12 3V3 | 3V3 6 |
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# +────────────+────────────+
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#
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# ___
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# td_p_pd──|___|───td_p────||────ORANGE/WHITE (RJ45 3)
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# 1k0 | 1u
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# ─
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# | | 100
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# ─
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# ___ |
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# td_n_pu──|___|───td_n────||────ORANGE (RJ45 6)
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# 1k0 1u
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#
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#
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# ___
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# rd_p_pd──|___|───rd_p────||────GREEN/WHITE (RJ45 1)
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# 1k0 | 1u
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# ─
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# | | 100
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# ─
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# ___ |
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# rd_n_pu──|___|───rd_n────||────GREEN (RJ45 2)
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# 1k0 1u
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#
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#
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# Alternate wiring using a transformer (both channels are identical):
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# ___
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# rd_p_pd──|___|───rd_p─────, ,────GREEN/WHITE (RJ45 1)
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# 1k0 | *_) || (_*
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# ─ _) || (_
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# | | 100 _) || (_
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# ─ _) || (_
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# ___ | _) || (_
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# rd_n_pu──|___|───rd_n─────' '────GREEN (RJ45 2)
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# 1k0
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#
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raw_eth = [
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("raw_eth", 0,
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Subsignal("td_p", Pins("pmodb:0"), IOStandard("LVCMOS33")),
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Subsignal("td_n", Pins("pmodb:1"), IOStandard("LVCMOS33")),
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Subsignal("rd_p", Pins("pmodb:2"), IOStandard("LVDS_25"), Misc("PULLDOWN")),
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Subsignal("rd_n", Pins("pmodb:3"), IOStandard("LVDS_25"), Misc("PULLUP")),
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Subsignal("td_p_pd", Pins("pmodb:4"), IOStandard("LVCMOS33")),
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Subsignal("td_n_pu", Pins("pmodb:5"), IOStandard("LVCMOS33")),
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Subsignal("rd_p_pd", Pins("pmodb:6"), IOStandard("LVCMOS33")),
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Subsignal("rd_n_pu", Pins("pmodb:7"), IOStandard("LVCMOS33")),
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),
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]
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(BaseSoC):
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def __init__(self, sys_clk_freq=int(50e6), with_raw_ethernet=True, **kwarg):
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analyzer_signals = []
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# BaseSoC ----------------------------------------------------------------------------------
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super().__init__(**kwarg
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)
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self.platform.add_extension(raw_eth)
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# Etherbone on 'raw' ethernet --------------------------------------------------------------
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if with_raw_ethernet:
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eth_raw_pads = self.platform.request("raw_eth")
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self.crg.clock_domains.cd_eth_raw = ClockDomain()
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self.crg.clock_domains.cd_eth_raw_tx = ClockDomain()
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self.crg.clock_domains.cd_eth_raw_rx = ClockDomain()
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self.comb += [
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self.crg.cd_eth_raw_rx.clk.eq(self.crg.cd_eth_raw.clk),
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self.crg.cd_eth_raw_tx.clk.eq(self.crg.cd_eth_raw.clk),
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]
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self.crg.pll.create_clkout(self.crg.cd_eth_raw, 40e6)
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self.submodules.ethphy = ethphy = LiteEthPHYETHERNET(
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pads = eth_raw_pads, refclk_cd="eth_raw",
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with_hw_init_reset = False)
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self.add_etherbone(name="etherbone", phy=self.ethphy, buffer_depth=255,
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ip_address="192.168.2.51", phy_cd="eth_raw")
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analyzer_signals += [
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ethphy.rx.fsm,
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ethphy.tx.fsm,
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ethphy.rx.rx_i,
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ethphy.tx.tx,
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]
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self.comb += [
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eth_raw_pads.td_p_pd.eq(0),
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eth_raw_pads.td_n_pu.eq(1),
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eth_raw_pads.rd_p_pd.eq(0),
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eth_raw_pads.rd_n_pu.eq(1),
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]
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# Analyzer ---------------------------------------------------------------------------------
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ethcore = self.ethcore_etherbone
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etherbone = self.etherbone
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals + [
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self.ethphy.sink,
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self.ethphy.source,
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# MAC.
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ethcore.mac.core.sink.valid,
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ethcore.mac.core.sink.ready,
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ethcore.mac.core.source.valid,
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ethcore.mac.core.source.payload,
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ethcore.mac.core.source.ready,
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# ARP.
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ethcore.arp.rx.sink.valid,
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ethcore.arp.rx.sink.ready,
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ethcore.arp.tx.source.valid,
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ethcore.arp.tx.source.ready,
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# IP.
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ethcore.ip.rx.sink.valid,
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ethcore.ip.rx.sink.ready,
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ethcore.ip.tx.source.valid,
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ethcore.ip.tx.source.ready,
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# UDP.
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ethcore.udp.rx.sink.valid,
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ethcore.udp.rx.sink.ready,
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ethcore.udp.tx.source.valid,
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ethcore.udp.tx.source.ready,
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# Etherbone.
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etherbone.packet.rx.sink.valid,
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etherbone.packet.rx.sink.ready,
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etherbone.packet.rx.fsm,
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etherbone.packet.tx.source.valid,
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etherbone.packet.tx.source.ready,
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etherbone.packet.tx.fsm,
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etherbone.record.receiver.fsm,
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etherbone.record.sender.fsm
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],
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depth=1024 * 8, trigger_depth=256)
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# Main ---------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Arty A7")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--toolchain", default="vivado", help="FPGA toolchain (vivado, symbiflow or yosys+nextpnr).")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
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target_group.add_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).")
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target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
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ethopts = target_group.add_mutually_exclusive_group()
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ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
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ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
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ethopts.add_argument("--raw-eth", action="store_true", help="use raw 10BASET ethernet on PMODA")
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target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
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target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
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sdopts = target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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target_group.add_argument("--sdcard-adapter", type=str, help="SDCard PMOD adapter (digilent or numato).")
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target_group.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.")
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target_group.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
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target_group.add_argument("--with-pmod-gpio", action="store_true", help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
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builder_args(parser)
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soc_core_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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assert not (args.with_etherbone and args.eth_dynamic_ip)
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soc = BenchSoC(
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variant = args.variant,
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toolchain = args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)),
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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eth_ip = args.eth_ip,
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eth_dynamic_ip = args.eth_dynamic_ip,
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with_jtagbone = args.with_jtagbone,
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with_spi_flash = args.with_spi_flash,
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with_pmod_gpio = args.with_pmod_gpio,
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with_raw_ethernet = args.raw_eth,
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**soc_core_argdict(args)
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)
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if args.sdcard_adapter == "numato":
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soc.platform.add_extension(digilent_arty._numato_sdcard_pmod_io)
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else:
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soc.platform.add_extension(digilent_arty._sdcard_pmod_io)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
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if args.build:
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builder.build(**builder_kwargs)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if args.flash:
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prog = soc.platform.create_programmer()
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prog.flash(0, builder.get_bitstream_filename(mode="flash"))
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if __name__ == "__main__":
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main()
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