Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

README: add 1000BaseX phy

This commit is contained in:
Florent Kermarrec 2018-06-29 14:47:22 +02:00
parent a2dbdd6d2b
commit ba2fdc532d
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README
View File

@ -32,6 +32,7 @@ design flow by generating the verilog rtl that you will use as a standard core.
PHY: PHY:
- MII / RMII - MII / RMII
- GMII / RGMII - GMII / RGMII
- 1000BaseX
Core: Core:
- MAC with various interfaces (to soft core or hardware stack) - MAC with various interfaces (to soft core or hardware stack)
- ARP - ARP
@ -55,7 +56,6 @@ LiteEth is already used in commercial and open-source designs:
- optimize ressources on HW ICMP and Etherbone (parameters buffering) - optimize ressources on HW ICMP and Etherbone (parameters buffering)
- add standardized interfaces (AXI, Avalon-ST) - add standardized interfaces (AXI, Avalon-ST)
- add DMA interface to MAC - add DMA interface to MAC
- add SGMII PHYs
- add more documentation - add more documentation
- ... See below Support and consulting :) - ... See below Support and consulting :)