mac/crc: Cleanup and try to move data-path connection outside of FSM for timings.
This commit is contained in:
Florent Kermarrec
parent
b22ac619ab
commit
bbdd6835aa
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@ -152,16 +152,20 @@ class LiteEthMACCRC32Inserter(LiteXModule):
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# # #
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# Parameters.
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data_width = len(sink.data)
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ratio = 32//data_width
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assert data_width in [8, 32, 64]
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crc = LiteEthMACCRC32(data_width)
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fsm = FSM(reset_state="IDLE")
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self.submodules += crc, fsm
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# crc packet checksum
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crc_packet = Signal(crc.width)
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last_be = Signal().like(sink.last_be)
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# Signals.
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crc_packet = Signal(32)
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last_be = Signal(data_width//8)
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# CRC32 Generator.
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self.crc = crc = LiteEthMACCRC32(data_width)
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# FSM.
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self.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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crc.reset.eq(1),
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sink.ready.eq(1),
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@ -170,22 +174,23 @@ class LiteEthMACCRC32Inserter(LiteXModule):
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NextState("COPY"),
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)
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)
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fsm.act("COPY",
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crc.ce.eq(sink.valid & source.ready),
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self.comb += [
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crc.data.eq(sink.data),
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crc.be.eq(sink.last_be),
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]
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fsm.act("COPY",
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crc.ce.eq(sink.valid & source.ready),
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sink.connect(source),
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source.last.eq(0),
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source.last_be.eq(0),
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If(sink.last,
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# Fill the empty space of the last data word with the
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# beginning of the crc value
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# Fill the empty space of the last data word with the beginning of the CRC value.
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[If(sink.last_be[e],
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source.data.eq(Cat(sink.data[:(e+1)*8],
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crc.value)[:data_width])) for e in range(data_width//8)],
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# If the whole crc value fits in the last sink paket, signal the
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# end. This also means the next state is idle
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If((data_width == 64) & (sink.last_be <= 0xF),
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# If the whole crc value fits in the last sink packet, signal the end. This also
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# means the next state is idle
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If((data_width == 64) & (sink.last_be <= 0xf),
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source.last.eq(1),
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source.last_be.eq(sink.last_be << (data_width//8 - 4))
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),
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@ -194,7 +199,7 @@ class LiteEthMACCRC32Inserter(LiteXModule):
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),
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If(sink.valid & sink.last & source.ready,
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If((data_width == 64) & (sink.last_be <= 0xF),
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If((data_width == 64) & (sink.last_be <= 0xf),
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NextState("IDLE"),
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).Else(
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NextValue(crc_packet, crc.value),
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@ -207,7 +212,6 @@ class LiteEthMACCRC32Inserter(LiteXModule):
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)
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)
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)
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ratio = crc.width//data_width
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if ratio > 1:
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cnt = Signal(max=ratio, reset=ratio-1)
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cnt_done = Signal()
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@ -216,7 +220,9 @@ class LiteEthMACCRC32Inserter(LiteXModule):
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chooser(crc_packet, cnt, source.data, reverse=True),
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If(cnt_done,
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source.last.eq(1),
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If(source.ready, NextState("IDLE"))
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If(source.ready,
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NextState("IDLE")
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)
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)
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)
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self.comb += cnt_done.eq(cnt == 0)
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@ -234,7 +240,9 @@ class LiteEthMACCRC32Inserter(LiteXModule):
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source.last_be.eq(last_be),
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[If(last_be[e],
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source.data.eq(crc_packet[-(e+1)*8:])) for e in range(data_width//8)],
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If(source.ready, NextState("IDLE"))
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If(source.ready,
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NextState("IDLE")
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)
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)
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# MAC CRC32 Checker --------------------------------------------------------------------------------
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@ -267,17 +275,16 @@ class LiteEthMACCRC32Checker(LiteXModule):
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# # #
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# Parameters.
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data_width = len(sink.data)
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ratio = ceil(32/data_width)
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assert data_width in [8, 32, 64]
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crc = LiteEthMACCRC32(data_width)
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self.submodules += crc
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ratio = ceil(crc.width/data_width)
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fifo = ResetInserter()(stream.SyncFIFO(description, ratio + 1))
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self.submodules += fifo
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# CRC32 Checker.
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self.crc = crc = LiteEthMACCRC32(data_width)
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fsm = FSM(reset_state="RESET")
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self.submodules += fsm
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# FIFO.
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self.fifo = fifo = ResetInserter()(stream.SyncFIFO(description, ratio + 1))
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fifo_in = Signal()
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fifo_out = Signal()
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@ -293,6 +300,8 @@ class LiteEthMACCRC32Checker(LiteXModule):
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self.sink.ready.eq(fifo_in),
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]
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# FSM.
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self.fsm = fsm = FSM(reset_state="RESET")
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fsm.act("RESET",
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crc.reset.eq(1),
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fifo.reset.eq(1),
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@ -310,10 +319,10 @@ class LiteEthMACCRC32Checker(LiteXModule):
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)
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last_be = Signal().like(sink.last_be)
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crc_error = Signal()
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self.comb += fifo.source.connect(source, omit={"valid", "ready", "last", "last_be"})
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fsm.act("COPY",
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fifo.source.ready.eq(fifo_out),
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source.valid.eq(sink.valid & fifo_full),
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source.payload.eq(fifo.source.payload),
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If(data_width <= 32,
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source.last.eq(sink.last),
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@ -350,7 +359,7 @@ class LiteEthMACCRC32Checker(LiteXModule):
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# If the last sink word contains both data and the crc value, shift out
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# the last value here. Can only happen for data_width == 64
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fsm.act("COPY_LAST",
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fifo.source.connect(source),
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fifo.source.connect(source, keep={"valid", "ready", "last"}),
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source.error.eq(fifo.source.error | Replicate(crc_error, data_width//8)),
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source.last_be.eq(last_be),
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If(source.valid & source.ready,
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