phy/k7_1000basex: Improve TX/RX init and add TX/RX polarity support.
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5400515a1e
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be9f26e876
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@ -51,7 +51,7 @@ class K7_1000BASEX(LiteXModule):
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dw = 8
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tx_clk_freq = 125e6
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rx_clk_freq = 125e6
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def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, with_csr=True):
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def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, with_csr=True, rx_polarity=0, tx_polarity=0):
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pcs = PCS(lsb_first=True)
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self.submodules += pcs
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@ -597,7 +597,7 @@ class K7_1000BASEX(LiteXModule):
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i_RXELECIDLEMODE = 0b11,
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# Receive Ports - RX Polarity Control Ports
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i_RXPOLARITY = 0,
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i_RXPOLARITY = rx_polarity,
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# Receive Ports - RX gearbox ports
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i_RXSLIDE = 0,
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@ -719,7 +719,7 @@ class K7_1000BASEX(LiteXModule):
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i_TXPDELECIDLEMODE = 0,
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# Transmit Ports - TX Polarity Control Ports
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i_TXPOLARITY = 0,
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i_TXPOLARITY = tx_polarity,
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# Transmit Ports - TX Receiver Detection Ports
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i_TXDETECTRX = 0,
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@ -765,11 +765,14 @@ class K7_1000BASEX(LiteXModule):
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self.comb += rx_mmcm_locked.eq(rx_mmcm.locked)
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# Transceiver init
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tx_init = GTXTXInit(sys_clk_freq, buffer_enable=True)
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tx_init = ResetInserter()(GTXTXInit(sys_clk_freq, buffer_enable=True))
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self.submodules += tx_init
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self.comb += [
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tx_init.reset.eq(self.crg_reset),
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pll.reset.eq(tx_init.pllreset),
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tx_init.plllock.eq(pll.lock),
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tx_reset.eq(tx_init.gtXxreset | self.crg_reset)
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tx_reset.eq(tx_init.gtXxreset),
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tx_init.Xxresetdone.eq(1), # FIXME.
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]
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self.sync += tx_mmcm_reset.eq(~pll.lock)
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tx_mmcm_reset.attr.add("no_retiming")
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@ -778,8 +781,10 @@ class K7_1000BASEX(LiteXModule):
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rx_init = ResetInserter()(GTXRXInit(sys_clk_freq, buffer_enable=True))
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self.submodules += rx_init
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self.comb += [
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rx_init.reset.eq(~tx_init.done),
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rx_reset.eq(rx_init.gtXxreset | self.crg_reset)
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rx_init.reset.eq(~tx_init.done | self.crg_reset),
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rx_init.plllock.eq(pll.lock),
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rx_reset.eq(rx_init.gtXxreset),
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rx_init.Xxresetdone.eq(1), # FIXME.
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]
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ps_restart = PulseSynchronizer("eth_tx", "sys")
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self.submodules += ps_restart
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